[coreboot-gerrit] Change in coreboot[master]: Documentation: Advertise support for OpenSBI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34690 )

Change subject: Documentation: Advertise support for OpenSBI
......................................................................

Documentation: Advertise support for OpenSBI

Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195
Signed-off-by: Patrick Rudolph 
---
M Documentation/arch/riscv/index.md
M Documentation/mainboard/sifive/hifive-unleashed.md
2 files changed, 16 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34690/1

diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md
index 9a5de34..528b691 100644
--- a/Documentation/arch/riscv/index.md
+++ b/Documentation/arch/riscv/index.md
@@ -23,8 +23,20 @@
 ## Additional payload handoff requirements
 The location of cbmem should be placed in a node in the FDT.

+## OpenSBI
+In case the payload doesn't install it's own SBI, like the [RISCV-PK] does,
+[OpenSBI] can be used instead.
+It's loaded into RAM after coreboot has finished loading the payload.
+coreboot then will jump to OpenSBI providing a pointer to the real payload,
+which OpenSBI will jump to once the SBI is installed.
+
+Besides providing SBI it also sets protected memory regions and provides
+a platform independend console.
+
+The OpenSBI code is always run in M mode.
+
 ## Trap delegation
-Traps are delegated in the ramstage.
+Traps are delegated to the payload.

## SMP within a stage
 At the beginning of each stage, all harts save 0 are spinning in a loop on
@@ -44,3 +56,6 @@
 will panic if possible, but behavior is largely undefined.

Only hart 0 runs through most of the code in each stage.
+
+[RISCV-PK]: https://github.com/riscv/riscv-pk
+[OpenSBI]: https://github.com/riscv/opensbi
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index 495dade..4dbbf0e 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -17,7 +17,6 @@
 - Provide serial number to payload (e.g. in device tree)
 - Implement instruction emulation
 - Support for booting Linux on RISC-V
-- Add support to run OpenSBI payload in m-mode
 - SMP support in trap handler

## Configuration