[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset...

[Subrata Banik (Code Review)]

Subrata Banik has uploaded a new patch set (#3) to the change originally created by Usha P. ( https://review.coreboot.org/c/coreboot/+/40363 )

Change subject: soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values
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soc/intel/common/systemagent: Add new PCIEXBAR register LENGTH offset values

Add PCIEXBAR register LENGTH offset values to accommodate new SoC
implementation.

Changes:
1. The major delta is 0x60:PCIEXBAR register LENGTH offset definition has
been changed for latest SoC.

2. Common code takes care of setting the right value for pciex length.

TEST=Able to build CNL, SKL, APL platforms.

Change-Id: I75619be7614f58c96670ef86485d49d4da06ad91
Signed-off-by: Usha P 
---
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
3 files changed, 37 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/40363/3