[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: update memory cfg for Tiger Lake

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40061 )

Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake
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Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... 
File src/soc/intel/tigerlake/meminit.c:

https://review.coreboot.org/c/coreboot/+/40061/1/src/soc/intel/tigerlake/mem... 
PS1, Line 234: mem_cfg->MrcSafeConfig = 0x1;
> Can you please push this as a separate change as it is required after 2527 lands.

Done