[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure L1Substates for PCH Root ports

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39412 )

Change subject: soc/intel/tigerlake: Configure L1Substates for PCH Root ports
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39412/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39412/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 118: if (config->PcieRpL1Substates[i])
             : 			params->PcieRpL1Substates[i] = config->PcieRpL1Substates[i] - 1;
> This is verified. if we don't assign, FSP use default values. […]

Ack