Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47182 )
Change subject: soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47182/1/src/soc/intel/tigerlake/elo... File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47182/1/src/soc/intel/tigerlake/elo... PS1, Line 53: PCIE_ROOT_PORT_STATUS
Ah yes, that simplifies this; I had forgotten that there was a capability reg for PM.
Done
https://review.coreboot.org/c/coreboot/+/47182/2/src/soc/intel/tigerlake/elo... File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47182/2/src/soc/intel/tigerlake/elo... PS2, Line 53: pci_dev_is_wake_source
nm you recently added the gsmi handler 😊
Ack
https://review.coreboot.org/c/coreboot/+/47182/4/src/soc/intel/tigerlake/elo... File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47182/4/src/soc/intel/tigerlake/elo... PS4, Line 51: uint32_t pme_status = pci_s_read_config32( : pme_map[i].devfn, : PCIE_ROOT_PORT_STATUS); : : if (pme_status == 0xFFFFFFFF || !(pme_status & BIT(16))) : continue; : : elog_add_event_wake(pme_map[i].wake_source, 0);
Not sure if you forgot to update the tigerlake in the same way as jasperlake.
Ack
https://review.coreboot.org/c/coreboot/+/47182/6/src/soc/intel/tigerlake/elo... File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47182/6/src/soc/intel/tigerlake/elo... PS6, Line 13: #define PCIE_ROOT_PORT_STATUS 0x60
Not required anymore.
Done