[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Modify CSE's PCI BAR address

[Sridhar Siricilla (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Tim Wawrzynczak, Rizwan Qureshi, Paul Menzel, Edward O'Callaghan, Subrata Banik, Sowmya V, Aamir Bohra, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44211

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Modify CSE's PCI BAR address
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soc/intel/cannonlake: Modify CSE's PCI BAR address

The patch modifies CSE's PCI BAR address to 0xfed1a000. Currently coreboot
uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses
0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with
0xfed1a000. This causes HECI command transactions to fail between FSP-M
call and postcar.

BRANCH=master
TEST=Verified sending HECI commands before and after FSP-M call on hatch.

Signed-off-by: Sridhar Siricilla 
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
---
M src/soc/intel/cannonlake/include/soc/iomap.h
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44211/2