Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )
Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@58 PS3, Line 58: MTRR: WB selected as default type.
I don't see any Type 1 MTRRs in here. […]
Please check the mask value for MTRR: 5 its basically ignoring WC to accommodate the BIOS MTRRs
MTRR: Removing WRCOMB type. WB/UC MTRR counts: 9/10 > 8. MTRR: default type WB/UC MTRR counts: 6/9. MTRR: WB selected as default type. MTRR: 0 base 0x0000000077000000 mask 0x00003fffff000000 type 0 MTRR: 1 base 0x0000000078000000 mask 0x00003ffffe000000 type 0 MTRR: 2 base 0x000000007a000000 mask 0x00003fffff000000 type 0 MTRR: 3 base 0x000000007b800000 mask 0x00003fffff800000 type 0 MTRR: 4 base 0x000000007c000000 mask 0x00003ffffc000000 type 0 MTRR: 5 base 0x0000000080000000 mask 0x00003fff80000000 type 0