Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35523 )
Change subject: mb/acer: Add Acer Aspire VN7-572G ......................................................................
Patch Set 21:
(6 comments)
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@9 PS20, Line 9: Adds
Add
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@12 PS20, Line 12: -Some amount of booting
Please be more specific.
With TianoCore as the payload, the last line of the log is "jumping to bootcode at..." SeaBIOS halts with an "unexpected APIC exception." Regardless, I have no graphics.
I initially wrote that line when I figured that something ultimately stopped TianoCore from loading, but I don't actually know if it's meant to be logging. I tried SeaBIOS only because I know that it logs to CBMEM.
Now I'm trying to get graphics working so that I can see what it's doing. I've extracted a VBT from the vendor BIOS (4 KB) to try instead of the one I retrieved from in Linux (6 KB) and I'll build another image.
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@15 PS20, Line 15: Assumed working:
Untested?
I haven't successfully booted into an OS yet, so while the console log says that it loaded the verb tables, yes, it's untested.
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@19 PS20, Line 19: Tianocore
TianoCore
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@11 PS20, Line 11: Works: : -Some amount of booting : -2/4 RAM slots : : Assumed working: : -Audio : : Does not work: : -Loading payload (tried Tianocore (at least no logging is occurring) : and SeaBIOS master (halts after unexpected APIC exception) : -Display (tried FSP GOP + VBT as well as OptionROM) : -Remaining RAM slots (need other SPD addresses. : These could be 0x51 and 0x53) : -Some PCIe stuff (some lspci devices aren't found and are disabled) : -TPM ("tis_probe: No TPM device found" but : "_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0")? : : Unknown: : -EC stuff (assumed from gpe0_{sts,en}[x]: 00000000) : -Microcode update (FIT states a size of 0, update is skipped)
Please add a space after the “bullet point”.
Done
https://review.coreboot.org/c/coreboot/+/35523/20//COMMIT_MSG@32 PS20, Line 32:
One blank line is enough.
Done