[coreboot-gerrit] Change in coreboot[master]: src/mainboard/{intel/google}: Include ASL for additional PCI segment

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, HAOUAS Elyes,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41012

to look at the new patch set (#3).

Change subject: src/mainboard/{intel/google}: Include ASL for additional PCI segment
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src/mainboard/{intel/google}: Include ASL for additional PCI segment

This patch allows mainboard to include static ASL for TBT PCI segment

extracted build/dsdt.aml

Device (PCI1)
{
    Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */)  // _HID: Hardware ID
    Name (_CID, EisaId ("PNP0A03") /* PCI Bus */)  // _CID: Compatible ID
    Name (_SEG, One)  // _SEG: PCI Segment
    Name (_UID, One)  // _UID: Unique ID
....
}

Change-Id: I3601aa4e9002334fd80fc86ced9e1df2afc739b5
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/deltaur/dsdt.asl
M src/mainboard/google/volteer/dsdt.asl
M src/mainboard/intel/tglrvp/dsdt.asl
3 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41012/3