[coreboot-gerrit] Change in coreboot[master]: cpu/intel/slot_1: Cache romstage XIP execution

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37164 )

Change subject: cpu/intel/slot_1: Cache romstage XIP execution
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cpu/intel/slot_1: Cache romstage XIP execution

Change-Id: I19fc31a0fe71c5d0c6845a8680e267a0bf5f1a8f
Signed-off-by: Arthur Heymans 
---
M src/cpu/intel/slot_1/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/37164/1

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 7919974..a8d90e8 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -27,6 +27,7 @@
    select UDELAY_TSC
    select TSC_MONOTONIC_TIMER
    select UNKNOWN_TSC_RATE
+	select SETUP_XIP_CACHE

config DCACHE_RAM_BASE
    hex