[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure L1Substates for PCH Root ports

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39412 )

Change subject: soc/intel/tigerlake: Configure L1Substates for PCH Root ports
......................................................................

Patch Set 4: Code-Review+1

(3 comments)

https://review.coreboot.org/c/coreboot/+/39412/3/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/39412/3/src/soc/intel/tigerlake/chi... 
PS3, Line 131: 	}PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
> space required after that close brace '}'

Ack

https://review.coreboot.org/c/coreboot/+/39412/3/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39412/3/src/soc/intel/tigerlake/fsp... 
PS3, Line 136: 	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
> braces {} are not necessary for single statement blocks

Ack

https://review.coreboot.org/c/coreboot/+/39412/3/src/soc/intel/tigerlake/fsp... 
PS3, Line 137: 		params->PcieRpL1Substates[i] = get_l1_substate_control(config->PcieRpL1Substates[i]);
> line over 96 characters

Ack