[coreboot-gerrit] Change in coreboot[master]: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

[Arthur Heymans (Code Review)]

Attention is currently required from: Arthur Heymans, Nico Huber, Angel Pons, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna).
Hello build bot (Jenkins), Nico Huber, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52942

to look at the new patch set (#2).

Change subject: cpu/intel/socket_p: Increase DCACHE_RAM_SIZE
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cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.

This fixes building when some debug options are enabled.

Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans 
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M src/cpu/intel/socket_p/Kconfig
M src/mainboard/lenovo/t400/Kconfig
2 files changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52942/2