Attention is currently required from: Arthur Heymans, Nico Huber, Angel Pons, Alexander Couzens, Patrick Rudolph, Swift Geek (Sebastian Grzywna).

Arthur Heymans uploaded patch set #2 to this change.

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cpu/intel/socket_p: Increase DCACHE_RAM_SIZE

The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.

This fixes building when some debug options are enabled.

Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/intel/socket_p/Kconfig
M src/mainboard/lenovo/t400/Kconfig
2 files changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/52942/2

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