Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34931 )
Change subject: qcs405: Add 500 ms delay ......................................................................
Patch Set 1: Code-Review-1
(3 comments)
https://review.coreboot.org/c/coreboot/+/34931/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34931/1//COMMIT_MSG@7 PS1, Line 7: qcs405: Add 500 ms delay Please be specific:
Delay writing DDR training data to SPI flash
Is that the correct prefix?
https://review.coreboot.org/c/coreboot/+/34931/1//COMMIT_MSG@10 PS1, Line 10: to the spi flash. Actual delay has to be calculated based Why does it need to be delayed?
https://review.coreboot.org/c/coreboot/+/34931/1/src/soc/qualcomm/common/qcl... File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/34931/1/src/soc/qualcomm/common/qcl... PS1, Line 86: //Add 500 ms delay Space after `//`. But the comment is useless, as the code is self-explanatory. Please add the reasoning in a comment, why such a long delay is needed.