[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

[Subrata Banik (Code Review)]

Hello Furquan Shaikh, Wonkyu Kim, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44014

to look at the new patch set (#2).

Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
......................................................................

src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

This patch ensures that the TSEG region is only mapped as cacheable so
that one can perform SMRAM relocation faster.

Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for
ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code
exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved)
and other ranges as reserve alone.

TEST=Able to build and boot ICL, TGL RVP.

Without this CL :

PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a

With this CL :

PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9
PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a
PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b

Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/systemagent/systemagent.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/2