[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Select CPU_INTEL_COMMON

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45041 )

Change subject: soc/intel/xeon_sp: Select CPU_INTEL_COMMON
......................................................................

soc/intel/xeon_sp: Select CPU_INTEL_COMMON

This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select
CPU_INTEL_COMMON directly, to avoid dependency problems.

Tested with BUILD_TIMELESS=1: Without including the config file in the
coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical.

Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041
Reviewed-by: Jonathan Zhang 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jonathan Zhang: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index a4274df..31d12fc 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -31,6 +31,7 @@
    select ARCH_VERSTAGE_X86_32
    select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
    select BOOT_DEVICE_SUPPORTS_WRITES
+	select CPU_INTEL_COMMON
    select SOC_INTEL_COMMON
    select SOC_INTEL_COMMON_RESET
    select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS