Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/27356 )
Change subject: riscv: add spin lock support ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spin... File src/arch/riscv/include/arch/smp/spinlock.h:
https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spin... PS2, Line 30: } while (atomic_cas(&lock->lock, 0, -1)); As far as I understand it, CAS is not a native operation on RISC-V. What does this compile to?
https://review.coreboot.org/#/c/27356/2/src/arch/riscv/include/arch/smp/spin... PS2, Line 39: Some primitives are missing, compared to the x86 pendant, but I think it's ok to add them later, when they're needed.