Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43958 )
Change subject: soc/mediatek/mt8192: Add PLL and clock init support ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll... File src/soc/mediatek/mt8192/pll.c:
https://review.coreboot.org/c/coreboot/+/43958/1/src/soc/mediatek/mt8192/pll... PS1, Line 114: MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3),
line over 96 characters
Could you please fix this?
MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3),
Alternatively, since "clk_cfg_0" is repeated, we can consider modify the MUX_UPD macro so that this line can be simplified to
MUX_UPD(TOP_BUS_AXIMEM_SEL, 0, 24, 3, clk_cfg_update, 3),
Here the second argument "0" will be expanded to clk_cfg_0, clk_cfg_0_set and clk_cfg_0_clr.