1 comment:
File src/soc/mediatek/mt8192/pll.c:
Patch Set #1, Line 114: MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr, 24, 3, clk_cfg_update, 3),
line over 96 characters
Could you please fix this?
MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, clk_cfg_0_set, clk_cfg_0_clr,
24, 3, clk_cfg_update, 3),
Alternatively, since "clk_cfg_0" is repeated, we can consider modify the MUX_UPD macro so that this line can be simplified to
MUX_UPD(TOP_BUS_AXIMEM_SEL, 0, 24, 3, clk_cfg_update, 3),
Here the second argument "0" will be expanded to clk_cfg_0, clk_cfg_0_set and clk_cfg_0_clr.
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