Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )
Change subject: soc/intel/tigerlake: Configure TCSS setting ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/chi... PS3, Line 233: TcssAuxOri Why do these have to be done by FSP? These are documented EDS registers which can be set by coreboot.
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38624/3/src/soc/intel/tigerlake/fsp... PS3, Line 141: memcpy(params->IomTypeCPortPadCfg, config->IomTypeCPortPadCfg, : sizeof(config->IomTypeCPortPadCfg)); Have you tried doing: memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
to see if it boots fine without the assert? and ensure that the required pads are configured before calling into FSP-S?