Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37928 )
Change subject: [WIP]mb/intel/tglrvp: Add correct memory SPD settings ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@6 PS2, Line 6: : [WIP] There is a WIP label in Gerrit.
https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@9 PS2, Line 9: Tigerlake Tiger Lake
https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@10 PS2, Line 10: for MRC boot config. Fits on the line above.
https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@11 PS2, Line 11: Please elaborate a little more, how you implement this.
https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@14 PS2, Line 14: tigerlake Tiger Lake
https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/spd/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... PS2, Line 18: One space?