Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37928 )
Change subject: [WIP]mb/intel/tglrvp: Add correct memory SPD settings ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... PS2, Line 23: static const u8 dq_map[8][2][8] = { : //Controller 0 : { { 0, 1, 6, 7, 3, 2, 5, 4 }, // Byte 0 : { 15, 8, 9, 14, 12, 11, 10, 13 } }, // Byte 1 : { { 11, 12, 8, 15, 9, 14, 10, 13 }, // Byte 2 : { 3, 4, 7, 0, 6, 1, 5, 2 } }, // Byte 3 : { { 4, 5, 3, 2, 7, 1, 0, 6 }, // Byte 4 : { 11, 10, 12, 13, 8, 9, 14, 15 } }, // Byte 5 : { { 12, 11, 8, 13, 14, 15, 9, 10 }, // Byte 6 : { 4, 7, 3, 2, 1, 6, 0, 5 } }, // Byte 7 : //Controller 1 : { { 11, 10, 9, 8, 12, 13, 15, 14 }, // Byte 0 ChB! : { 4, 5, 6, 7, 3, 2, 0, 1 } }, // Byte 1 ChB! : { { 0, 7, 1, 6, 3, 5, 2, 4 }, // Byte 2 : { 9, 8, 10, 11, 14, 15, 13, 12 } }, // Byte 3 : { { 4, 5, 6, 1, 3, 2, 7, 0 }, // Byte 4 : { 10, 13, 12, 11, 14, 9, 15, 8 } }, // Byte 5 : { { 10, 12, 9, 15, 8, 11, 13, 14 }, // Byte 6 : { 3, 4, 1, 2, 6, 0, 5, 7 } } // Byte 7 : }; : : /* DQS CPU<>DRAM map */ : static const u8 dqs_map[8][2] = { : // Ch 0 1 2 3 : { 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 }, // Controller 0 : { 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 } // Controller 1 : }; is this for LPDDR4? Can we use memory.c for this data? And we need to support DDR4 with mainboard config
https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... PS2, Line 71: #if 0 : mem_cfg->MemorySpdPtr00 = spd_ptr; : mem_cfg->MemorySpdPtr02 = spd_ptr; : mem_cfg->MemorySpdPtr04 = spd_ptr; : mem_cfg->MemorySpdPtr06 = spd_ptr; : #endif : mem_cfg->MemorySpdPtr08 = spd_ptr; : mem_cfg->MemorySpdPtr10 = spd_ptr; : mem_cfg->MemorySpdPtr12 = spd_ptr; : mem_cfg->MemorySpdPtr14 = spd_ptr; : : mem_cfg->SpdAddressTable[0] = 0x0; : mem_cfg->SpdAddressTable[1] = 0x0; : mem_cfg->SpdAddressTable[2] = 0x0; : mem_cfg->SpdAddressTable[3] = 0x0; : } else { : mem_cfg->MemorySpdPtr00 = 0; : mem_cfg->MemorySpdPtr01 = 0; : mem_cfg->MemorySpdPtr10 = 0; : mem_cfg->MemorySpdPtr11 = 0; : : mem_cfg->SpdAddressTable[0] = 0xA0; : mem_cfg->SpdAddressTable[1] = 0xA2; : mem_cfg->SpdAddressTable[2] = 0xA4; : mem_cfg->SpdAddressTable[3] = 0xA6; : } Need to support DDR4 case