Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(2 comments)
devicetree looks much cleaner!! 😎
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 23: pcie_clk_src_usage suggestion: `convert_clk_src_to_fsp`
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 153: !is_dev_enabled(dev) ? 0 : : pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS); suggestion: I think this reads easier inverted, i.e., ``` m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev) ? pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS) : 0; ```