Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35230 )
Change subject: src/soc/intel/common/block/cse: Add print_me_fw_version() to cse lib ......................................................................
Patch Set 11:
(82 comments)
https://review.coreboot.org/c/coreboot/+/35230/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35230/2//COMMIT_MSG@12 PS2, Line 12:
Tested how?
Done
https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 786: struct version {
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 786: struct version {
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 787: uint16_t minor;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 787: uint16_t minor;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 788: uint16_t major;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 788: uint16_t major;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 789: uint16_t build;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 789: uint16_t build;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 790: uint16_t hotfix;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 790: uint16_t hotfix;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 791: } __packed;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 791: } __packed;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 793: struct fw_ver_resp {
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 793: struct fw_ver_resp {
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 794: struct mkhi_hdr hdr;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 794: struct mkhi_hdr hdr;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 795: struct version code;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 795: struct version code;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 796: struct version rec;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 796: struct version rec;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 797: struct version fitc;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 797: struct version fitc;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 798: } __packed;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 798: } __packed;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 800: union me_hfs hfsts1;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 800: union me_hfs hfsts1;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 801: const struct mkhi_hdr fw_ver_msg = {
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 801: const struct mkhi_hdr fw_ver_msg = {
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 802: .group_id = MKHI_GEN_GROUP_ID,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 802: .group_id = MKHI_GEN_GROUP_ID,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 803: .command = MKHI_GET_FW_VERSION,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 803: .command = MKHI_GET_FW_VERSION,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 804: };
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 804: };
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 805: struct fw_ver_resp resp;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 805: struct fw_ver_resp resp;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 806: size_t resp_size = sizeof(resp);
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 806: size_t resp_size = sizeof(resp);
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 808: /* Ignore if UART debugging is disabled */
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 809: if (!CONFIG(CONSOLE_SERIAL))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 809: if (!CONFIG(CONSOLE_SERIAL))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 810: return;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 810: return;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 812: hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 812: hfsts1.data = me_read_config32(PCI_ME_HFSTS1);
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 814: /*
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 815: * Prerequisites:
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 816: * 1) HFSTS1 Current Working State is Normal
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 817: * 2) HFSTS1 Current Operation Mode is Normal
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 818: * 3) It's after DRAM INIT DONE message (taken care of by calling it
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 819: * during ramstage
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 820: */
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 821: if ((hfsts1.fields.working_state != ME_HFS_CWS_NORMAL) ||
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 821: if ((hfsts1.fields.working_state != ME_HFS_CWS_NORMAL) ||
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 822: (hfsts1.fields.operation_mode != ME_HFS_MODE_NORMAL))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 822: (hfsts1.fields.operation_mode != ME_HFS_MODE_NORMAL))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 823: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 823: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 825: heci_reset();
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 825: heci_reset();
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 827: if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 827: if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 828: HECI_MKHI_ADDR))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 828: HECI_MKHI_ADDR))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 829: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 829: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 831: if (!heci_receive(&resp, &resp_size))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 831: if (!heci_receive(&resp, &resp_size))
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 832: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 832: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 834: if (resp.hdr.result)
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 834: if (resp.hdr.result)
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 835: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 835: goto fail;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 837: printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 837: printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major,
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 838: resp.code.minor, resp.code.hotfix, resp.code.build);
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 839: return;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 839: return;
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 842: printk(BIOS_DEBUG, "ME: Version: Unavailable\n");
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https://review.coreboot.org/c/coreboot/+/35230/1/src/soc/intel/common/block/... PS1, Line 842: printk(BIOS_DEBUG, "ME: Version: Unavailable\n");
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