EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... PS9, Line 122: struct {
BTW, I think we don't need PCIE_RP_ENABLED. […]
SG! Let me try this.
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
I think this will have to be config->pcie_rp[i].clk_req - 1. Same for clk_src below.
Why need -1? The schematic is from 0-9, device tree is 0-9 as well.