2 comments:
File src/soc/intel/alderlake/chip.h:
Patch Set #9, Line 122: struct {
BTW, I think we don't need PCIE_RP_ENABLED. […]
SG! Let me try this.
File src/soc/intel/alderlake/romstage/fsp_params.c:
Patch Set #9, Line 40: config->PcieRp[i].clkreq
I think this will have to be config->pcie_rp[i].clk_req - 1. Same for clk_src below.
Why need -1? The schematic is from 0-9, device tree is 0-9 as well.
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