Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40572 )
Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios ......................................................................
mb/intel/jasperlake_rvp: Configure SoC specific gpios
This patch configures all SoC related gpios as per mainboard schematics. Till now, we were relying on FSP to do SoC specific gpio programming but now we'll program all gpios from mainboard. This will remove ambiguity of gpio programming done by FSP and coreboot will do full gpio programming
Programming gpios of following IPs - I2C - Emmc - Display - CPU specific gpio (SLP lines) - Cnvi
BUG=None BRANCH=None TEST=compile coreboot and checked that all IPs functionality working.
Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c 1 file changed, 146 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/40572/1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 9b86839..d9eb35f 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -7,14 +7,37 @@
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill other gpio configuration */
/* WWAN_WAKE_N */ PAD_CFG_GPI_SCI(GPP_A10, NONE, DEEP, LEVEL, INVERT),
+ /* DDSP_HPD_B */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* EDP_HPD */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* M.2_WWAN_DISABLE_N */ PAD_CFG_GPO(GPP_A19, 1, PLTRST),
+ /* VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + + /* PCIE_X4_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + + /* AP_SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST),
@@ -30,7 +53,7 @@ /* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
- /*PCH_INT_ODL*/ + /* DDP_HDMI_HPD_C */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
/* WWAN_PERST_N */ @@ -60,18 +83,114 @@ /* I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* WWAN_FCP_OFF_N */ PAD_CFG_GPO(GPP_E3, 1, PLTRST),
+ /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1), + + /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1), + + /* DDPC_CTRLCLK */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* CNV_BRI_DT_R */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + + /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* CNV_RGI_DT_R */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + + /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + + /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + + /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + + /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + + /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + + /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + + /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + + /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + + /* EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + + /* EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + + /* EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + + /* SD_CD# */ + PAD_CFG_NF(GPP_G5, UP_20K, PWROK, NF1), + + /* SD_WP */ + PAD_CFG_NF(GPP_G7, DN_20K, PWROK, NF1), + /*FPS_INT*/ PAD_CFG_GPI_APIC(GPP_H0, NONE, PLTRST, LEVEL, INVERT),
+ /* SD_PWR_EN_B */ + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1) + + /* CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), + /* WWAN EN GPIO */ PAD_CFG_GPO(GPP_H7, 1, PLTRST),
+ /* CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* M.2_BT_I2S2_SCLK */ PAD_CFG_GPI(GPP_H11, NONE, PLTRST),
+ /* CNV_RF_RESET */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF2), + /*PCH_INT_ODL*/ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP, EDGE_SINGLE, INVERT),
@@ -103,10 +222,10 @@ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2),
/* I2S1_SFRM */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
/* I2S1_TXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
/* WWAN RST_N */ PAD_CFG_GPO(GPP_S0, 1, DEEP), @@ -123,6 +242,29 @@ /* DMIC_DATA_0 */ PAD_CFG_NF(GPP_S7, UP_20K, DEEP, NF2),
+ /* AP_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + + /* GPP_GPD1/ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + + /* EC_AP_WAKE_ODL */ + PAD_CFG_NF(GPD2, NONE, DEEP, NF1), + + /* EC_AP_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + + /* AP_SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + + /* AP_SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + + /* WLAN_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + /* virtual GPIO for SD card detect */ + PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, DEEP), };
/* Early pad configuration in bootblock */