Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40002 )
Change subject: mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode ......................................................................
mb/google/cyan: Switch eMMC and SD from ACPI to PCI mode
Braswell boards don't work well with the eMMC and SD controller in ACPI in payloads other than depthcharge - SeaBIOS requires an onerous workaround, and Tianocore can't see the devices at all. To make the common use-case work better, switch from ACPI mode to PCI mode.
Test: build/boot cyan variants with SeaBIOS and Tianocore payloads, verify eMMC and SD card visible and bootable.
Change-Id: I71947603e22a37fe2c8ef4eaac8a3aa0d0ed1cec Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/google/cyan/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/40002/1
diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index d5f7a3f..5df1a5a 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -19,7 +19,7 @@ # Set the parameters for SiliconInit ############################################################
- register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdSdcardMode" = "PCH_PCI_MODE" register "PcdEnableHsuart0" = "0" register "PcdEnableHsuart1" = "1" register "PcdEnableAzalia" = "1" @@ -36,7 +36,7 @@ register "PcdEnableI2C6" = "0" register "PunitPwrConfigDisable" = "0" # Enable SVID register "ChvSvidConfig" = "SVID_PMIC_CONFIG" - register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdEmmcMode" = "PCH_PCI_MODE" register "PcdUsb3ClkSsc" = "1" register "PcdDispClkSsc" = "1" register "PcdSataClkSsc" = "1" @@ -84,10 +84,10 @@ # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
- # Enable devices in ACPI mode + # Enable LPSS and LPE devices in ACPI mode register "lpss_acpi_mode" = "1" - register "emmc_acpi_mode" = "1" - register "sd_acpi_mode" = "1" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" register "lpe_acpi_mode" = "1"
# Disable SLP_X stretching after SUS power well fail.