Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38147 )
Change subject: soc/intel/tigerlake: Enable Audio on TGL ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/chi... PS8, Line 113: PchHdaIDispCodecDisconnect
Here, default value of 0 means connected and 1 is disconnected. […]
Ack
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/38147/8/src/soc/intel/tigerlake/rom... PS8, Line 108: m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2; : m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7; : m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4; : m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3; : m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Let's not do this here. I think doing the pinmux config in coreboot should be fine.
Furquan, i tried the same experiment we did on volteer on tglrvp, I am not able to get the board booting without these configs. I am following up on how it worked on volteer and not on tglrvp. one thing i can think of the change in FSP versions. Will follow up on that. But in the meantime can we have this included here for the bootable recipe ? Without this I am not able get tglrvp booting.