2 comments:
File src/soc/intel/tigerlake/chip.h:
Patch Set #8, Line 113: PchHdaIDispCodecDisconnect
Here, default value of 0 means connected and 1 is disconnected. […]
Ack
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:
m_cfg->PchHdaAudioLinkDmicClkAPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6;
m_cfg->PchHdaAudioLinkDmicClkBPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2;
m_cfg->PchHdaAudioLinkDmicDataPinMux[0] = GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7;
m_cfg->PchHdaAudioLinkDmicClkAPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4;
m_cfg->PchHdaAudioLinkDmicClkBPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3;
m_cfg->PchHdaAudioLinkDmicDataPinMux[1] = GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5;
Let's not do this here. I think doing the pinmux config in coreboot should be fine.
Furquan, i tried the same experiment we did on volteer on tglrvp, I am not able to get the board booting without these configs. I am following up on how it worked on volteer and not on tglrvp. one thing i can think of the change in FSP versions. Will follow up on that. But in the meantime can we have this included here for the bootable recipe ? Without this I am not able get tglrvp booting.
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