[coreboot-gerrit] Change in coreboot[master]: [WIP]mb/intel/tglrvp: Add correct memory SPD settings

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37928 )

Change subject: [WIP]mb/intel/tglrvp: Add correct memory SPD settings
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Patch Set 3:

(5 comments)

https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@6 
PS2, Line 6: 
           : [WIP]
> There is a WIP label in Gerrit.

Ack

https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@9 
PS2, Line 9: Tigerlake
> Tiger Lake

Ack

https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@10 
PS2, Line 10: for MRC boot config.
> Fits on the line above.

Ack

https://review.coreboot.org/c/coreboot/+/37928/2//COMMIT_MSG@14 
PS2, Line 14: tigerlake
> Tiger Lake

Ack

https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... 
File src/mainboard/intel/tglrvp/spd/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/37928/2/src/mainboard/intel/tglrvp/... 
PS2, Line 18:
> One space?

Ack