Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45229 )
Change subject: mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant ......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/3/Documentation/mainboard/sup... PS3, Line 37: - S3 resume not working
Sorry, I may be just blind... […]
Done
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... File Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md:
https://review.coreboot.org/c/coreboot/+/45229/4/Documentation/mainboard/sup... PS4, Line 39: failed to be initialize
Add some notes about using IGD for computaion, please, if you're able to resolve the issue
Done
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h:
https://review.coreboot.org/c/coreboot/+/45229/3/src/mainboard/supermicro/x1... PS3, Line 8:
I have added some comments below; would be great if you could provide the raw inteltool output; just […]
inteltool dunp: https://pastebin.com/yzfpLx9f
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... File src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 14: # Additional FSP Configuration : # This board has an IGD with no output. : register "PrimaryDisplay" = "Display_Auto" :
Sorry for the confusion; I haven't thought about that case. […]
Done
https://review.coreboot.org/c/coreboot/+/45229/4/src/mainboard/supermicro/x1... PS4, Line 18: # PCIe configuration : # Enable i210-AT (GbE) : register "PcieRpEnable[0]" = "1" : register "PcieRpEnable[1]" = "1" : : # Enable M.2 : register "PcieRpEnable[4]" = "1" : : # Enable ASpeed PCI bridge : register "PcieRpEnable[6]" = "1" : : # Enable JPCIE1 : register "PcieRpEnable[8]" = "1" :
The PcieRpEnable fsp settings are going to be set via the on/off setting in the devicetree in the ne […]
Done