Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
soc/intel/braswell: Increase dcache size
Increase the DRAM cache size for Braswell to address the compilation error
Cache as RAM area too full
when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage.
BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards
Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen shchen@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ae4fc21..4eb810e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -93,7 +93,7 @@
config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE