Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
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Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro...
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro...
PS23, Line 154: is_dev_enabled(dev)
There is no PCIE 6.x to present more CPU_RP... If you look up the device tree.. […]
At least for TGL, the EDS says that the CPU RP 6.0 does not support bifurcation. So, all lanes can be controlled only by controller 6.0. You will have to check the same for ADL to see what controllers exist and what lane configuration is supported.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
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