Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45333 )
Change subject: soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port ......................................................................
soc/amd/picasso: Add UPD for support force USB3 to Gen1 by port
Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.
BUG=b:167651308 BRANCH=zork TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Edward O'Callaghan quasisec@chromium.org Reviewed-by: Sam McNally sammc@google.com --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c 2 files changed, 15 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Sam McNally: Looks good to me, approved
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index a39549e..f4233de 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -37,6 +37,17 @@ uint8_t tx_res_tune; };
+/* force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1, etc */ +union __packed usb3_force_gen1 { + struct { + uint8_t xhci0_port0:1; + uint8_t xhci0_port1:1; + uint8_t xhci0_port2:1; + uint8_t xhci0_port3:1; + } ports; + uint8_t usb3_port_force_gen1_en; +}; + #define USB_PORT_COUNT 6
enum sd_emmc_driver_strength { @@ -190,8 +201,10 @@ */ uint16_t init_khz_preset; } emmc_config; - + /* set xhci0 from gen2 to gen1 */ uint8_t xhci0_force_gen1; + /* Force USB3 port to gen1, bit0 - controller0 Port0, bit1 - Port1 */ + union usb3_force_gen1 usb3_port_force_gen1;
uint8_t has_usb2_phy_tune_params; struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT]; diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 95e691d..973bb87d4 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -111,6 +111,7 @@ ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);
scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1; + scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1.usb3_port_force_gen1_en;
if (cfg->has_usb2_phy_tune_params) { for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {