[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail: Add MRC SMBus workaround

[Máté Kukri (Code Review)]

Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44092 )

Change subject: soc/intel/baytrail: Add MRC SMBus workaround
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44092/4/src/soc/intel/baytrail/roms... 
File src/soc/intel/baytrail/romstage/raminit.c:

https://review.coreboot.org/c/coreboot/+/44092/4/src/soc/intel/baytrail/roms... 
PS4, Line 170: if (mp->mainboard.spd_addrs[i]) {
             : 				i2c_eeprom_read(mp->mainboard.spd_addrs[i],
             : 					0, SPD_SIZE, spd_buf[i]);
             : 				/* NOTE: the MRC expects both SPD pointers
             : 					to match */
             : 				mp->mainboard.dram_data[i] = spd_buf;
             : 			}
> A single DIMM in channel 1 would surely fail. […]

(The 0xF0 and 0xF1 are fake SPD addresses the MRC's main function sets as markers for in memory SPD for channel 0 and 1.)