Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40572 )
Change subject: mb/intel/jasperlake_rvp: Configure SoC specific gpios ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... File src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c:
https://review.coreboot.org/c/coreboot/+/40572/5/src/mainboard/intel/jasperl... PS5, Line 23: /* VCCIN_AUX_VID0 */ : PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), : : /* VCCIN_AUX_VID1 */ : PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), : : /* WLAN_CLKREQ_ODL */ : PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), : : /* PCIE_X4_CLKREQ_ODL */ : PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), : : /* AP_SLP_S0_L */ : PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), : : /* PLT_RST_L */ : PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
I think these configuration are better to be handled on SoC code. […]
Ack Hi Rizwan,
Thank you for suggestion. Can we check in this patch and work on moving SoC specific gpios into soc code later? I'll put to do in file and commit msg.