Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37115 )
Change subject: sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode ......................................................................
Patch Set 11:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... File src/southbridge/intel/bd82x6x/me.h:
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 193: #define CMOS_ME_STATE_DISABLED 1 Use tabs for alignment as above.
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 250: int Make that boolean?
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... File src/southbridge/intel/bd82x6x/me_8.x.c:
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 637: printk(BIOS_CRIT, "%s: mbp is not ready!\n", __func__); Unrelated.
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 758: BIOS_SPEW Level *info* or *debug* would be more useful I guess.
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 799: printk(BIOS_ERR, "ME: failed to enter Soft Temporary Disable mode\n"); {} around this branch.
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 821: BIOS_INFO Level *notice* would be more appropriate in my opinion.
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... File src/southbridge/intel/bd82x6x/me_common.c:
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 21: int boolean
https://review.coreboot.org/c/coreboot/+/37115/11/src/southbridge/intel/bd82... PS11, Line 28: #endif Why is the distinction needed? Is it run in romstage and ramstage?