Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Nick Vaccaro, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40061
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: update memory cfg for Tiger Lake ......................................................................
soc/intel/tigerlake: update memory cfg for Tiger Lake
Update mem cfg on Tiger Lake Platform to use DisableDimmCh# UPD
BUG=150357377 BRANCH=none TEST= build volteer and boot to kernel
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/40061/2