coreboot-gerrit April 2025

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[M] Change in coreboot[main]: src/vendorcode/amd/fsp: Update for glinda
by Maximilian Brune (Code Review) 02 Apr '25

02 Apr '25

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87086?usp=email ) Change subject: src/vendorcode/amd/fsp: Update for glinda ...................................................................... src/vendorcode/amd/fsp: Update for glinda Update params for Glinda SoC according to glinda FSP. TEST=Build & boot AMD birman plus board & make sure dmidecode -t 17 shows more accurate info. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I110039e160ada8899e3a414fcf32ee8236b510b4 --- M src/vendorcode/amd/fsp/common/dmi_info.h M src/vendorcode/amd/fsp/glinda/soc_dmi_info.h 2 files changed, 59 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/87086/1 diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h index 390732d..1f94a32 100644 --- a/src/vendorcode/amd/fsp/common/dmi_info.h +++ b/src/vendorcode/amd/fsp/common/dmi_info.h @@ -157,7 +157,11 @@ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. OUT CHAR8 SerialNumber[9]; ///< Serial Number. +#if CONFIG(SOC_AMD_GLINDA) + OUT CHAR8 PartNumber[31]; ///< Part Number. +#else OUT CHAR8 PartNumber[21]; ///< Part Number. +#endif OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. OUT UINT32 ExtSize; ///< Extended Size. OUT UINT16 ConfigSpeed; ///< Configured memory clock speed @@ -183,8 +187,58 @@ #endif } __packed TYPE17_DMI_INFO; +/// DMI Type 19 - Memory Array Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, + ///< of a range of memory mapped to the + ///< specified physical memory array. + OUT UINT32 EndingAddr; ///< The physical ending address of the + ///< last kilobyte of a range of addresses + ///< mapped to the specified physical memory array. + OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated + ///< with the physical memory array to which this + ///< address range is mapped. + OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that + ///< form a single row of memory for the address + ///< partition defined by this structure. + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. + OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. +} TYPE19_DMI_INFO; + +///DMI Type 20 - Memory Device Mapped Address +typedef struct { + OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range + ///< of memory mapped to the referenced Memory Device. + OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with + ///< the Memory Device structure to which this address + ///< range is mapped. + OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated + ///< with the Memory Array Mapped Address structure to + ///< which this device address range is mapped. + OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory + ///< Device in a row of the address partition. + OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in + ///< an interleave. + OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the + ///< referenced Memory Device that are accessed in a + ///< single interleaved transfer. + OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the referenced Memory Device. + OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of + ///< a range of addresses mapped to the referenced Memory Device. +} TYPE20_DMI_INFO; + /// Collection of pointers to the DMI records typedef struct { OUT TYPE16_DMI_INFO T16; ///< Type 16 struc OUT TYPE17_DMI_INFO T17[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL]; ///< Type 17 struc +#if CONFIG(SOC_AMD_GLINDA) + OUT TYPE19_DMI_INFO T19[AGESA_STRUCT_T19_REGION_SUPPORTED]; + OUT TYPE20_DMI_INFO T20[AGESA_STRUCT_SOCKET_COUNT][AGESA_STRUCT_CHANNELS_PER_SOCKET][AGESA_STRUCT_DIMMS_PER_CHANNEL][AGESA_STRUCT_T20_REGION_SUPPORTED]; ///< Type 20 struc +#endif } DMI_INFO; diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h index 08f5f5c..f854059 100644 --- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h +++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h @@ -2,15 +2,16 @@ /* * These definitions are used to describe memory modules physical layout - * TODO: Update for Glinda */ #ifndef SOC_DMI_INFO_H #define SOC_DMI_INFO_H -#define AGESA_STRUCT_SOCKET_COUNT 2 ///< Number of sockets in AGESA FSP DMI T17 table -#define AGESA_STRUCT_CHANNELS_PER_SOCKET 8 ///< Channels per socket in AGESA FSP DMI T17 table -#define AGESA_STRUCT_DIMMS_PER_CHANNEL 4 ///< DIMMs per channel in AGESA FSP DMI T17 table +#define AGESA_STRUCT_SOCKET_COUNT 4 ///< Number of sockets in AGESA FSP DMI T17 table +#define AGESA_STRUCT_CHANNELS_PER_SOCKET 16 ///< Channels per socket in AGESA FSP DMI T17 table +#define AGESA_STRUCT_DIMMS_PER_CHANNEL 2 ///< DIMMs per channel in AGESA FSP DMI T17 table +#define AGESA_STRUCT_T19_REGION_SUPPORTED 3 ///< Max SMBIOS T19 Memory Region count +#define AGESA_STRUCT_T20_REGION_SUPPORTED 3 ///< Max SMBIOS T20 Memory Region count #define SMBIOS_3_2_3_3_SUPPORT 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/87086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I110039e160ada8899e3a414fcf32ee8236b510b4 Gerrit-Change-Number: 87086 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: security/intel/txt: Verify Intel TXT required TPM2 indices presence
by Julius Werner (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Arthur Heymans, Felix Singer, Filip Lewiński, Krystian Hebel, Martin Roth, Michał Kopeć, Yu-Ping Wu. Julius Werner has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82417?usp=email ) Change subject: security/intel/txt: Verify Intel TXT required TPM2 indices presence ...................................................................... Patch Set 21: (1 comment) File src/security/intel/txt/common.c: https://review.coreboot.org/c/coreboot/+/82417/comment/bff28d16_cd0369fd?us… : PS21, Line 627: #if CONFIG(TPM2) You can put this in a C `if()`, you don't need to use a preprocessor guard. It will compile out the code if that Kconfig is disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/82417?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5b4267b2d51e21cfa514e96301f30ebf7437c470 Gerrit-Change-Number: 82417 Gerrit-PatchSet: 21 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 23:14:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: google/chromeec: Add function to report the SKU ID
by Julius Werner (Code Review) 02 Apr '25

02 Apr '25

Attention is currently required from: Aamir Bohra, Boris Mittelberg, Caveh Jalali, Dinesh Gehlot, Eran Mitrani, Eric Lai, Hung-Te Lin, Jakub "Kuba" Czapiga, Jason Nien, Jayvik Desai, Kapil Porwal, Martin Roth, Nick Vaccaro, Paul Menzel, Pranava Y N, Subrata Banik, Subrata Banik, Tarun. Julius Werner has posted comments on this change by Aamir Bohra. ( https://review.coreboot.org/c/coreboot/+/86810?usp=email ) Change subject: google/chromeec: Add function to report the SKU ID ...................................................................... Patch Set 12: Code-Review+1 (1 comment) File src/ec/google/chromeec/Makefile.mk: https://review.coreboot.org/c/coreboot/+/86810/comment/836bf6cf_55c7b7d2?us… : PS12, Line 14: y > if you need google_chromeec_get_board_sku for platform w/ EC_GOOGLE_CHROMEEC_SMBIOS, then you can move google_chromeec_get_board_sku api into ec_chrome.c Whether we move the parts that are not supposed to be guarded by the Kconfig out into another file, or we remove the Kconfig switch from the file and instead introduce it as a CPP guard around one function, comes out to the same thing. I don't think there's anything wrong with the approach taken in this patch, it makes sense to keep both functions in that file because they're both related to SKU ID stuff (and it's nice when reading the code to get them both on one screen). Moving stuff that's guarded by a separate Kconfig out into a separate file sometimes makes sense, but there's no rule saying it must always be done that way — it comes down to the specific circumstances. -- To view, visit https://review.coreboot.org/c/coreboot/+/86810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I958cc88bf316dd2327b6545c5a37e8010e96c5d7 Gerrit-Change-Number: 86810 Gerrit-PatchSet: 12 Gerrit-Owner: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub "Kuba" Czapiga <czapiga(a)google.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Attention: Boris Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 22:47:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Aamir Bohra <aamirbohra(a)google.com>

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[M] Change in coreboot[main]: soc/intel/pantherlake: Add Touch Controller UPD and SoC config
by Jérémy Compostella (Code Review) 01 Apr '25

01 Apr '25

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85199?usp=email ) ( 35 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Add Touch Controller UPD and SoC config ...................................................................... soc/intel/pantherlake: Add Touch Controller UPD and SoC config This commit introduces the necessary changes to configure the Touch Host Controller User Platform Data (UPD) fields such as ThcAssignment, ThcMode, and ThcWakeOnTouch according to the specific SoC chip configuration derived from the devicetree. Key changes include: - Creation of override functions to supply SoC-specific configurations for the Touch Host Controller (THC). - Addition of a new SoC-specific THC header file. - Inclusion of a motherboard (MB)-specific THC header file. - Establishment of a build path to allow devicetree to leverage variant-specific defines. BUG=none TEST=Add CONFIG_DRIVERS_INTEL_TOUCH to fatcat board with the devicetree changes for touchscreen and/or touchpad, as well as proper CBI settings. Boot the board to OS and check that the THC SoC-specific info is generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/85199 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/Makefile.mk M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/fsp_params.c A src/soc/intel/pantherlake/include/soc/touch.h A src/soc/intel/pantherlake/touch.c 5 files changed, 134 insertions(+), 2 deletions(-) Approvals: Jérémy Compostella: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index f3403b5..e2f8dd7 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -43,6 +43,7 @@ ramstage-y += systemagent.c ramstage-y += tcss.c ramstage-y += xhci.c +ramstage-$(CONFIG_DRIVERS_INTEL_TOUCH) += touch.c smm-y += elog.c smm-y += gpio.c diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index cd91e31..eb702b7 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -26,6 +26,8 @@ #define MAX_SAGV_POINTS 4 #define MAX_HD_AUDIO_SDI_LINKS 2 +#define NUM_THC 2 + /* In-Band ECC Operation Mode */ enum ibecc_mode { IBECC_MODE_PER_REGION, @@ -539,6 +541,19 @@ uint16_t max_dram_speed_mts; + /* + * Touch Host Controller Mode + * Switch between Intel THC protocol and Industry standard HID protocols. + * 0x0:Thc, 0x1:HID over SPI, 0x2:HID over I2C + */ + uint8_t thc_mode[NUM_THC]; + + /* + * Touch Host Controller Wake On Touch + * Based on this setting vGPIO for given THC will be in native mode, and additional _CRS + * for wake will be exposed in ACPI + */ + bool thc_wake_on_touch[NUM_THC]; }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 7544894..cac866f 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -576,8 +576,15 @@ static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_pantherlake_config *config) { - s_cfg->ThcAssignment[0] = is_devfn_enabled(PCI_DEVFN_THC0) ? THC_0 : THC_NONE; - s_cfg->ThcAssignment[1] = is_devfn_enabled(PCI_DEVFN_THC1) ? THC_1 : THC_NONE; + for (size_t i = 0; i < NUM_THC; i++) { + if (!is_devfn_enabled(_PCI_DEVFN(THC, i))) { + s_cfg->ThcAssignment[i] = THC_NONE; + continue; + } + s_cfg->ThcAssignment[i] = THC_0 + i; + s_cfg->ThcMode[i] = config->thc_mode[i]; + s_cfg->ThcWakeOnTouch[i] = config->thc_wake_on_touch[i]; + } } static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/pantherlake/include/soc/touch.h b/src/soc/intel/pantherlake/include/soc/touch.h new file mode 100644 index 0000000..33b3d1d --- /dev/null +++ b/src/soc/intel/pantherlake/include/soc/touch.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PANTHERLAKE_TOUCH_H_ +#define _SOC_PANTHERLAKE_TOUCH_H_ + +/* For THC-I2C: */ + +/* + * I2C Standard Mode (100Kbps): + * Requested Connection Speed: 186A0 + * I2C Speed Mode: Standard (100Kbps) = 0x186A0 + * + * I2C Fast Mode (400Kbps): + * Requested Connection Speed: 61A80 + * I2C Speed Mode: Fast (400Kbps) = 0x612B0 + * + * I2C Fast-Plus Mode (1Mbps): + * Requested Connection Speed: F4240 + * I2C Speed Mode: Fast-Plus (1Mbps) = 0xF4240 + * FM SCL HIGH Period: 34 Fast Mode (FM) CLK Signal HIGH Period + * FM SCL LOW Period: 3E Fast Mode (FM) CLK Signal LOW Period + */ +#define SOC_PTL_THC_I2C_CONNECTION_SPEED_SM 0x186a0 +#define SOC_PTL_THC_I2C_CONNECTION_SPEED_FM 0x61a80 +#define SOC_PTL_THC_I2C_CONNECTION_SPEED_FMP 0xf4240 + +/* + * 0 = 7-bit Addressing Mode for HID-I2C (Default) + * 1 = 10-bit Addressing Mode for HID-I2C + */ +#define SOC_PTL_THC_I2C_ADDR_MODE 0 +#define SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD 0x267 +#define SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD 0x271 +#define SOC_PTL_THC_I2C_SM_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_SM_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_FM_SCL_HIGH_PERIOD 0x92 +#define SOC_PTL_THC_I2C_FM_SCL_LOW_PERIOD 0x9c +#define SOC_PTL_THC_I2C_FM_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_FM_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP 0 +#define SOC_PTL_THC_I2C_FMP_SCL_HIGH_PERIOD 0x34 +#define SOC_PTL_THC_I2C_FMP_SCL_LOW_PERIOD 0x3e +#define SOC_PTL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SCL_HIGH_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SCL_LOW_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SDA_HOLD_TX_PERIOD 0 +#define SOC_PTL_THC_I2C_HM_SDA_HOLD_RX_PERIOD 0 +#define SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_H_FP 0 + + +/* For THC-SPI: */ + +/* unit: ms */ +#define SOC_PTL_THC_RST_SEQ_DLY 300 + +/* The initial default speed is 17000000 Hz. */ +#define SOC_PTL_THC_CONNECTION_SPEED 17000000 + +/* 0 = no limit */ +#define SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ 0 +#define SOC_PTL_THC_PERFORMANCE_LIMIT 0 + +#endif /* _SOC_PANTHERLAKE_TOUCH_H_ */ diff --git a/src/soc/intel/pantherlake/touch.c b/src/soc/intel/pantherlake/touch.c new file mode 100644 index 0000000..ed475fe --- /dev/null +++ b/src/soc/intel/pantherlake/touch.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/touch/chip.h> +#include <soc/touch.h> + +/* SoC-specific THC-I2C config */ +const struct intel_thc_hidi2c_info *soc_get_thc_hidi2c_info(void) +{ + static const struct intel_thc_hidi2c_info soc_thc_hidi2c_info = { + .connection_speed = SOC_PTL_THC_I2C_CONNECTION_SPEED_FM, + .addr_mode = SOC_PTL_THC_I2C_ADDR_MODE, + .sm_scl_high_period = SOC_PTL_THC_I2C_SM_SCL_HIGH_PERIOD, + .sm_scl_low_period = SOC_PTL_THC_I2C_SM_SCL_LOW_PERIOD, + .sm_sda_hold_tx_period = SOC_PTL_THC_I2C_SM_SDA_HOLD_TX_PERIOD, + .sm_sda_hold_rx_period = SOC_PTL_THC_I2C_SM_SDA_HOLD_RX_PERIOD, + .fm_scl_high_period = SOC_PTL_THC_I2C_FM_SCL_HIGH_PERIOD, + .fm_scl_low_period = SOC_PTL_THC_I2C_FM_SCL_LOW_PERIOD, + .fm_sda_hold_tx_period = SOC_PTL_THC_I2C_FM_SDA_HOLD_TX_PERIOD, + .fm_sda_hold_rx_period = SOC_PTL_THC_I2C_FM_SDA_HOLD_RX_PERIOD, + .suppressed_spikes_s_f_fp = SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_S_F_FP, + .fmp_scl_high_period = SOC_PTL_THC_I2C_FMP_SCL_HIGH_PERIOD, + .fmp_scl_low_period = SOC_PTL_THC_I2C_FMP_SCL_LOW_PERIOD, + .fmp_sda_hold_tx_period = SOC_PTL_THC_I2C_FMP_SDA_HOLD_TX_PERIOD, + .fmp_sda_hold_rx_period = SOC_PTL_THC_I2C_FMP_SDA_HOLD_RX_PERIOD, + .hm_scl_high_period = SOC_PTL_THC_I2C_HM_SCL_HIGH_PERIOD, + .hm_scl_low_period = SOC_PTL_THC_I2C_HM_SCL_LOW_PERIOD, + .hm_sda_hold_tx_period = SOC_PTL_THC_I2C_HM_SDA_HOLD_TX_PERIOD, + .hm_sda_hold_rx_period = SOC_PTL_THC_I2C_HM_SDA_HOLD_RX_PERIOD, + .suppressed_spikes_h_fp = SOC_PTL_THC_I2C_SUPPRESSED_SPIKES_H_FP, + }; + return &soc_thc_hidi2c_info; +} + +/* SoC-specific THC-SPI config */ +const struct intel_thc_hidspi_info *soc_get_thc_hidspi_info(void) +{ + static const struct intel_thc_hidspi_info soc_thc_hidspi_info = { + .connection_speed = SOC_PTL_THC_CONNECTION_SPEED, + .write_mode = HIDSPI_WRITE_MODE_MULTI_SINGLE_SPI, + .limit_packet_size = SOC_PTL_THC_HIDSPI_LIMIT_PKT_SZ, + .performance_limit = SOC_PTL_THC_PERFORMANCE_LIMIT, + .reset_sequencing_delay = SOC_PTL_THC_RST_SEQ_DLY, + }; + return &soc_thc_hidspi_info; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85199?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fb62eaadc03b9a17e94609b97c686518150e2e Gerrit-Change-Number: 85199 Gerrit-PatchSet: 37 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/touch/touch.c: https://review.coreboot.org/c/coreboot/+/87085/comment/540c8eb1_cea95d98?us… : PS1, Line 197: /* NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode > Missing line break before NOTE. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 21:51:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[S] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers, Jérémy Compostella. Hello Intel coreboot Reviewers, Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/87085?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... drivers/intel/touch: Conditionally add ACPI _PRW based on wake source This change addresses an issue in the touch driver where the ACPI _PRW method was added unconditionally. The ACPI _PRW method should only be generated when an Interrupt() resource is used in the _CRS method. When a GpioInt() resource is used instead, the _PRW method is not required. The ACPI generation code has been updated to conditionally add the _PRW method based on whether the wake source is a GPIO interrupt or an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin is specified, which is consistent with ACPI requirements. BUG=none TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has the necessary touch configurations with wake support. Verify that the THC ACPI tables are correctly generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 --- M src/drivers/intel/touch/touch.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/87085/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik, Wonkyu Kim. Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/85200?usp=email ) Change subject: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad ...................................................................... Patch Set 37: (3 comments) File src/mainboard/google/fatcat/variants/fatcat/fw_config.c: https://review.coreboot.org/c/coreboot/+/85200/comment/085a363f_566526f1?us… : PS26, Line 483: PAD_CFG_GPI_APIC_DRIVER > It is not because it is vGPIO. […] marked as resolved. File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85200/comment/f295c042_a77bc73a?us… : PS26, Line 333: GPE0_DW0_10 > Yes, GpioInt() is created for wake_gpio which will work in Driver mode. […] You are right about wake_gpe. Only when using Interrupt() in _CRS, the GPE event is used and need the GPE mapping bit in _PRW method. Also, the GPIO pad needs to be in ACPI mode. Currently, we use GpioInt() and PAD in Driver mode for THC. For touchpad in LPSS mode, we will still need to remap pmc_gpe0_dw0 to GPP_F group. The i2c generic driver uses _PRW and GPE. I removed the pmc_gpe0_dw0 override for vGPIO. Thanks for pointing this out. This is very helpful. File src/mainboard/google/fatcat/variants/fatcat/variant.c: https://review.coreboot.org/c/coreboot/+/85200/comment/dc771f38_70994455?us… : PS29, Line 33: if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_I2C))) : config->thc_mode[0] = THC_HID_I2C_MODE; : else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_THC_SPI))) : config->thc_mode[0] = THC_HID_SPI_MODE; : else if (fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_GSPI))) > It is a bit complicated on Fatcat board constraint regarding of overriding pmc_gpe0_dw0. […] removed the override for pmc_gpe0_dw0 to vGPIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/85200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Gerrit-Change-Number: 85200 Gerrit-PatchSet: 37 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 21:47:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Cliff Huang <cliff.huang(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Jérémy Compostella (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Cliff Huang, Intel coreboot Reviewers. Jérémy Compostella has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/drivers/intel/touch/touch.c: https://review.coreboot.org/c/coreboot/+/87085/comment/d0c47343_7cf931ab?us… : PS1, Line 197: /* NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode Missing line break before NOTE. -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Comment-Date: Tue, 01 Apr 2025 21:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Intel coreboot Reviewers. Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87085?usp=email ) Change subject: drivers/intel/touch: Conditionally add ACPI _PRW based on wake source ...................................................................... drivers/intel/touch: Conditionally add ACPI _PRW based on wake source This change addresses an issue in the touch driver where the ACPI _PRW method was added unconditionally. The ACPI _PRW method should only be generated when an Interrupt() resource is used in the _CRS method. When a GpioInt() resource is used instead, the _PRW method is not required. The ACPI generation code has been updated to conditionally add the _PRW method based on whether the wake source is a GPIO interrupt or an IRQ interrupt. Now, the _PRW method is only added when an IRQ pin is specified, which is consistent with ACPI requirements. BUG=none TEST=Configure the DRIVERS_INTEL_TOUCH option on a motherboard that has the necessary touch configurations with wake support. Verify that the THC ACPI tables are correctly generated in the SSDT. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 --- M src/drivers/intel/touch/touch.c 1 file changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/87085/1 diff --git a/src/drivers/intel/touch/touch.c b/src/drivers/intel/touch/touch.c index 0283312..f094683 100644 --- a/src/drivers/intel/touch/touch.c +++ b/src/drivers/intel/touch/touch.c @@ -194,14 +194,19 @@ touch_acpi_name(dev)); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); + /* NOTE: config->wake_gpio: uses GpioInt() in _CRS; PAD needs to be Driver Mode + * config->wake_irq: uses Interrupt() in _CRS; use GPE; PAD needs to be ACPI Mode + */ if (config->wake_gpio.pin_count) acpi_device_write_gpio(&config->wake_gpio); else if (config->wake_irq.pin) acpi_device_write_interrupt(&config->wake_irq); acpigen_write_resourcetemplate_footer(); - acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); - acpigen_write_PRW(config->wake_gpe, 3); + if (config->wake_irq.pin) { + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); + acpigen_write_PRW(config->wake_gpe, 3); + } } static void touch_generate_acpi_i2cdev_dsd(const struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/87085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56fc8486c7494ff37c1d580d57838fee286128a6 Gerrit-Change-Number: 87085 Gerrit-PatchSet: 1 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com> Gerrit-Attention: Intel coreboot Reviewers <intel_coreboot_reviewers(a)intel.com>

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[M] Change in coreboot[main]: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad
by Cliff Huang (Code Review) 01 Apr '25

01 Apr '25

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Paul Menzel, Pranava Y N, Subrata Banik, Wonkyu Kim. Hello Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Kyoung Il Kim, Pranava Y N, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85200?usp=email to look at the new patch set (#37). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad ...................................................................... mb/google/fatcat: Add Intel Touch support for touchscreen and touchpad This commit introduces support for touch functionalities on the Google Fatcat board( Please see docu # 818597). Changes include: - Configuration for building with the THC driver - Support for touchscreen devices in both THC-I2C and THC-SPI modes - Rework is necessary for touchscreen use in THC-SPI mode on Fatcat board - The ELAN BOM37A device is supported in THC-I2C mode - The ELAN BOM36 device is supported in THC-SPI mode - Support for the HYNITRON HFW68H touchpad device in THC-I2C mode - A rework is required to switch the interrupt pad from GPP_A13 to GPP_F18 for touchpad use in THC-I2C mode - Introduction of variant-specific touch.h header file - Wake support from S0ix state for both touchscreen and touchpad across multiple modes: LPSS-I2C, THC-I2C, and THC-SPI - PMC GPE DW0 is reconfigured to GPP_F for Touchpad in LPSS mode in variant.c for wake support BUG=none TEST= 1. Set the CBI firmware configuration for touchscreen to TOUCHSCREEN_LPSS_I2C and/or TOUCHPAD to TOUCHPAD_LPSS_I2C 2. Check the ACPI objects are generated in SSDT 3. The devices should be enumerated under the /sys/class/hidraw directory 4. The Touchscreen and/or touchpad should function properly The cursor on the screen should move accordingly 5. Test wake from S0ix state via touchscreen and touchpad inputs 6. Repeat the above for the THC CBI configurations: touchscreen: TOUCHSCREEN_THC_I2C touchpad: TOUCHPAD_THC_I2C Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/gpio.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb M src/mainboard/google/fatcat/variants/fatcat/variant.c 5 files changed, 183 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85200/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/85200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I865dbb9eed648c8f35c7f469b27a13be993ff479 Gerrit-Change-Number: 85200 Gerrit-PatchSet: 37 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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