Attention is currently required from: Martin L Roth.
Felix Held has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/84710?usp=email )
Change subject: Documentation/internals: Add devicetree language documentation
......................................................................
Patch Set 5:
(2 comments)
File Documentation/internals/devicetree_language.md:
https://review.coreboot.org/c/coreboot/+/84710/comment/152203fe_a404cc21?us… :
PS5, Line 447: /eSPI
eSPI doesn't support legacy DMA any more. ISA had it, and it was optional, but usually implemented in LPC. CB:87204
https://review.coreboot.org/c/coreboot/+/84710/comment/0ff30bd8_8ade6cf6?us… :
PS5, Line 974: Currently, only a single segment is supported
not true; we support more than one pci segment group. CB:87206
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87206?usp=email )
Change subject: doc/internals/devicetree_language: multiple segment groups supported
......................................................................
doc/internals/devicetree_language: multiple segment groups supported
coreboot supports more than just one PCI segment group by having more
than one domain in the devicetree, so update the PCI device description.
Change-Id: I9911b5e43732dd32638d540fcec6ca57b34d4fbc
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M Documentation/internals/devicetree_language.md
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/87206/1
diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index ab1b646..43a2233 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -973,11 +973,11 @@
Resources for all PCI devices are assigned automatically, or must be
assigned in code if they're non-standard.
-Currently, only a single segment is supported, but there is work to make
-multiple different segments supported, each with a bus 0. Because the
-bus is not specified, It's assumed that all pci devices that are not
-behind a pci bridge device are on bus 0. If there are additional pci
-busses in a chip, they can be added behind their bridge device.
+Only a single segment group is supported per domain, but there can be multiple
+domains to support the case of multiple segment groups, each with a bus 0.
+Because the bus is not specified, It's assumed that all pci devices that are
+not behind a pci bridge device are on bus 0. If there are additional pci busses
+in a chip, they can be added behind their bridge device.
Examples:
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Change subject: doc/internals/devicetree_language: describe I2C identifier
......................................................................
doc/internals/devicetree_language: describe I2C identifier
Even when the identifier of an I2C device doesn't have a '0x' prefix,
it's still interpreted as a hexadecimal number.
Change-Id: I0e5a7e39ac56e25499493a16eefa49e4f8d79337
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M Documentation/internals/devicetree_language.md
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/87205/1
diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index d189844..ab1b646 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -690,6 +690,8 @@
* Introduced in: Initial sconfig implementation, pre coreboot 4.0
* Usage: `device I2c <identifier> [alias <alias ID>] <status modifier> ... end`
+The identifier is the device's address encoded as hexadecimal number.
+
Example:
```text
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Change subject: doc/internals/devicetree_language: eSPI doesn't support legacy DRQ
......................................................................
doc/internals/devicetree_language: eSPI doesn't support legacy DRQ
In contracts to the ISA and LPC bus, eSPI doesn't support legacy
ISA-style DMA any more, so don't list eSPI as interface in the 'drq'
chapter.
The Intel document #841685 "Enhanced Serial Peripheral Interface (eSPI)
Interface Base Specification (for Client and Server Platforms)" revision
1.6 says this about the eSPI interface: "However, 8237 DMA and Firmware
Hub (FWH) are not supported over this interface."
Change-Id: I69d4b09688699dfc984a42671abfe3804d30ade9
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M Documentation/internals/devicetree_language.md
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/87204/1
diff --git a/Documentation/internals/devicetree_language.md b/Documentation/internals/devicetree_language.md
index 0609559..d189844 100644
--- a/Documentation/internals/devicetree_language.md
+++ b/Documentation/internals/devicetree_language.md
@@ -444,7 +444,7 @@
* Usage: `drq 0x<register #> = <drq line>`
Drq is used to configure a legacy DMA Request line register for a device
-on a legacy bus - ISA/LPC/eSPI.
+on a legacy bus - ISA/LPC.
The drq configuration is only allowed inside a pnp block.
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Change subject: doc/contributing/git_commit_messages: fix line length
......................................................................
doc/contributing/git_commit_messages: fix line length
The line length limit in the commit messages is 72 characters, not 75,
so fix the value in the documentation. The 72 characters also matches
what checkpatch checks for.
Change-Id: I2ec0fbd78fd0b054eae7bf9d6bd30580f47deb8f
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M Documentation/contributing/git_commit_messages.md
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/87203/1
diff --git a/Documentation/contributing/git_commit_messages.md b/Documentation/contributing/git_commit_messages.md
index 4addf4c..a007b2a 100644
--- a/Documentation/contributing/git_commit_messages.md
+++ b/Documentation/contributing/git_commit_messages.md
@@ -13,14 +13,14 @@
## Line length
- The subject line should be <= 65 characters, with an absolute maximum
- of 75 characters
-- Prose in the commit message should be <= 75 characters
-- If reflowing prose to 75 characters can reduce the length of the
+ of 72 characters
+- Prose in the commit message should be <= 72 characters
+- If reflowing prose to 72 characters can reduce the length of the
commit message by 2 or more lines, please reflow it. Using the entire
- 75 characters on a line when reasonable is recommended, but not
+ 72 characters on a line when reasonable is recommended, but not
required.
- Non-prose text in the body in the commit message does not need to be
- wrapped at 75 characters. Examples: URLs, compiler output, or poetry.
+ wrapped at 72 characters. Examples: URLs, compiler output, or poetry.
## Both Subject & body
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