coreboot-gerrit January 2025

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[XS] Change in coreboot[main]: soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible
by Yidi Lin (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85918?usp=email ) Change subject: soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible ...................................................................... soc/mediatek/common/dp: Use DP_WRITE2BYTE if possible This patch prevents wrong mask passing to mtk_dp_mask. TEST=emerge-rauru coreboot, check FW screen Change-Id: If8c801173089761db55992279045d053c60dcd86 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx_hal.c M src/soc/mediatek/common/dp/dptx_hal_common.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/85918/1 diff --git a/src/soc/mediatek/common/dp/dptx_hal.c b/src/soc/mediatek/common/dp/dptx_hal.c index 97578d2..f3a6a41 100644 --- a/src/soc/mediatek/common/dp/dptx_hal.c +++ b/src/soc/mediatek/common/dp/dptx_hal.c @@ -120,7 +120,7 @@ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, BIT(7), BIT(7)); DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020); - mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020, 0xfff); + DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020); mtk_dp_write_byte(mtk_dp, REG_3300_DP_ENCODER1_P0 + 1, 0x2, BIT(1) | BIT(0)); mtk_dp_write_byte(mtk_dp, REG_3364_DP_ENCODER1_P0 + 1, diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index 4d4b9b8..a5b342f 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -263,12 +263,12 @@ void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value) { - mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff); + DP_WRITE2BYTE(mtk_dp, REG_3364_DP_ENCODER1_P0, value); } void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value) { - mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff); + DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, value); } bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr, size_t length, -- To view, visit https://review.coreboot.org/c/coreboot/+/85918?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If8c801173089761db55992279045d053c60dcd86 Gerrit-Change-Number: 85918 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte
by Yidi Lin (Code Review) 09 Jan '25

09 Jan '25

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85917?usp=email ) Change subject: soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte ...................................................................... soc/mediatek/common/dp: Fix `mask` data type in mtk_dp_write_byte TEST=emerge-rauru coreboot Change-Id: I2762d6ca024d60663f6dae0db62a959a191adc02 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/dp/dptx_hal_common.c M src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/85917/1 diff --git a/src/soc/mediatek/common/dp/dptx_hal_common.c b/src/soc/mediatek/common/dp/dptx_hal_common.c index e8180e4..4d4b9b8 100644 --- a/src/soc/mediatek/common/dp/dptx_hal_common.c +++ b/src/soc/mediatek/common/dp/dptx_hal_common.c @@ -53,7 +53,7 @@ clrsetbits32(addr, mask, val & mask); } -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask) +void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask) { if (addr % 2) { mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12); diff --git a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h index 7ed41e8..7f0e30f 100644 --- a/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h +++ b/src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h @@ -69,7 +69,7 @@ void mtk_dp_phy_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); void mtk_dp_phy_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset); -void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask); +void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u8 mask); void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask); void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val); void dptx_hal_verify_clock(struct mtk_dp *mtk_dp); -- To view, visit https://review.coreboot.org/c/coreboot/+/85917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2762d6ca024d60663f6dae0db62a959a191adc02 Gerrit-Change-Number: 85917 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Enable SAGv
by Pranava Y N (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Bora Guvendik, Subrata Banik. Pranava Y N has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/coreboot/+/85272?usp=email ) Change subject: mb/google/fatcat: Enable SAGv ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I am seeing a boot time regression of 55ms w/ this CL. @bora.guvendik@intel.com can you please create a partner bug for this so that we can discuss further? -- To view, visit https://review.coreboot.org/c/coreboot/+/85272?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I340f4951fd33deadaac53edd30e2cf6bfc2a750b Gerrit-Change-Number: 85272 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 09:28:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Initialize MCUPM
by Yu-Ping Wu (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85888?usp=email ) Change subject: soc/mediatek/mt8196: Initialize MCUPM ...................................................................... Patch Set 2: (13 comments) File src/soc/mediatek/mt8196/include/soc/mcupm_plat.h: https://review.coreboot.org/c/coreboot/+/85888/comment/ee1b8c04_ed36f9c9?us… : PS2, Line 42: 1b What does this mean? https://review.coreboot.org/c/coreboot/+/85888/comment/624d7733_5dc8e77b?us… : PS2, Line 70: REPLACE_15 Please define a meaningful name. What does bit 15 mean? https://review.coreboot.org/c/coreboot/+/85888/comment/6a1ee285_35a743eb?us… : PS2, Line 84: SIZE Is this supposed to be `NUM`? From the comment, this is the number of slots, not the size of a slot. https://review.coreboot.org/c/coreboot/+/85888/comment/2f5d4429_9b5ed7c7?us… : PS2, Line 93: 0x1000BC7C What does this stand for? File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/f237061e_7c804626?us… : PS1, Line 39: /* set CPUEB_STATE_VALID = 1 */ : setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 1 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) == : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } : : /* set CPUEB_STATE_VALID = 0 */ : clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); : : /* polling CPUEB_STATE_FINISH_ACK = 0 */ : if (!retry(POLLING_ACK_TIME, : (read32p(SPM_MCUPM_SPMC_CON) & CPUEB_STATE_FINISH_ACK) != : CPUEB_STATE_FINISH_ACK, udelay(1))) { : printk(BIOS_WARNING, : "[EB_SPMC] Polling ACK timeout, %#x\n", : read32p(SPM_MCUPM_SPMC_CON)); : return -1; : } > What I mean is this. Then we use the same logic to set/clear CPUEB_STATE_VALID value. […] How about ``` static int set_cpueb_state(bool state_valid) { if (state_valid) clrbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); else setbits32p(SPM_MCUPM_SPMC_CON, CPUEB_STATE_VALID); ... } ``` File src/soc/mediatek/mt8196/mcupm.c: https://review.coreboot.org/c/coreboot/+/85888/comment/267ec204_ac2d37f1?us… : PS2, Line 16: Polling Poll https://review.coreboot.org/c/coreboot/+/85888/comment/c756e130_51007c44?us… : PS2, Line 20: WARNING Should this be `ERR`? https://review.coreboot.org/c/coreboot/+/85888/comment/78695baf_eba11f64?us… : PS2, Line 46: WARNING ERR? Same below. https://review.coreboot.org/c/coreboot/+/85888/comment/b3de61eb_76bb465d?us… : PS2, Line 65: eb_sleep_protect return eb_sleep_protect(); https://review.coreboot.org/c/coreboot/+/85888/comment/990693f3_1d2ad5e2?us… : PS2, Line 81: %s: Let's use `[EB_SPMC]` for consistency. https://review.coreboot.org/c/coreboot/+/85888/comment/68e83795_42b7532f?us… : PS2, Line 85: %s remove https://review.coreboot.org/c/coreboot/+/85888/comment/7b8bed1b_7541444f?us… : PS2, Line 124: %s() `%s:` https://review.coreboot.org/c/coreboot/+/85888/comment/c44af5bb_683ee963?us… : PS2, Line 127: %s() `%s:` -- To view, visit https://review.coreboot.org/c/coreboot/+/85888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I223f245d384f32d54f6170a28b29573638f77296 Gerrit-Change-Number: 85888 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 09:15:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: agogo <agogo.huang(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: Documentation/drivers/smmstore: Fix dead link
by Werner Zeh (Code Review) 09 Jan '25

09 Jan '25

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85916?usp=email ) Change subject: Documentation/drivers/smmstore: Fix dead link ...................................................................... Documentation/drivers/smmstore: Fix dead link The link to the document 'A Tour Beyond BIOS - Implementing UEFI Authenticated Variables in SMM with EDK II' is currently pointing to a dead location at Intel's website. Fix it by changing it to point at tianocore's github site and hope that this one will be more reliable over time. Change-Id: Ic6ba341cbd37edec142f8868ffe9ef677736b3dd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M Documentation/drivers/smmstore.md M Documentation/drivers/smmstorev2.md 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85916/1 diff --git a/Documentation/drivers/smmstore.md b/Documentation/drivers/smmstore.md index c9f0060..717beee 100644 --- a/Documentation/drivers/smmstore.md +++ b/Documentation/drivers/smmstore.md @@ -128,7 +128,7 @@ ## External links -* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDK II](https://github.com/tianocore-docs/Docs/raw/master/White_Papers/A_Tour_B… Note, this differs significantly from coreboot's implementation. diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index 6956cd4..af6e0ce 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -199,7 +199,7 @@ ## External links -* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_b… +* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDK II](https://github.com/tianocore-docs/Docs/raw/master/White_Papers/A_Tour_B… Note that this differs significantly from coreboot's implementation. -- To view, visit https://review.coreboot.org/c/coreboot/+/85916?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6ba341cbd37edec142f8868ffe9ef677736b3dd Gerrit-Change-Number: 85916 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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[S] Change in coreboot[main]: Documentation: Fix wrong link to commit message guidelines
by Werner Zeh (Code Review) 09 Jan '25

09 Jan '25

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85915?usp=email ) Change subject: Documentation: Fix wrong link to commit message guidelines ...................................................................... Documentation: Fix wrong link to commit message guidelines In the gerrit guidelines there is an old link pointing to the retired coreboot wiki (https://www.coreboot.org/Git#Commit_messages) when the commit message guidelines are referenced. Indeed this section was never ported over to the new documentation and is missing. This commit rewrites this guidelines and adds them as a new section based on what was in the wiki and updates the link accordingly. Change-Id: I1cd2b13da6fe59697d677c7350d73eda5d486544 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M Documentation/contributing/gerrit_guidelines.md 1 file changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85915/1 diff --git a/Documentation/contributing/gerrit_guidelines.md b/Documentation/contributing/gerrit_guidelines.md index ce6fa6f..2de1a39 100644 --- a/Documentation/contributing/gerrit_guidelines.md +++ b/Documentation/contributing/gerrit_guidelines.md @@ -304,7 +304,7 @@ the files that you’ve changed, and add those people. * Familiarize yourself with the coreboot [commit message -guidelines](https://www.coreboot.org/Git#Commit_messages), before pushing +guidelines](#commit-message-guidelines), before pushing patches. This will help to keep annoying requests to fix your commit message to a minimum. @@ -433,8 +433,50 @@ Requests for clarification and suggestions for updates to these guidelines should be sent to the coreboot mailing list at <coreboot(a)coreboot.org>. +Commit message guidelines +------------------------- +Git does not enforce a certain style for commit messages. For all aspects of +Git to work best with, it's important to follow these simple guidelines for +commit messages: + +- The first line of the commit message consists of a short + (less than 65 characters, absolute maximum is 75) summary +- The second line is empty (no whitespace at all) +- The third and any following number of lines contains a longer description + of the commit as is necessary, including relevant background information + and quite possibly rationale for why the issue was solved in this particular + way. These lines should never be longer than 75 characters. +- The next line is empty (no whitespace at all) +- An optional TEST= line which describes the test that was done in order to + validate the patch +- An optional BUG= line to reference to a bug (of [coreboot's bug tracker] or any + other) this patch resolves +- The next line is empty if the optional lines are used +- A Change-Id: line to let gerrit track this logical change +- A signed-off-by: line according to [Signed-off-by policy](#sign-off-procedure) + +Please do not create the Change-Id: and Signed-off-by: entries manually because +it is boring and error-prone. Instead, please install the commit-msg hook and +let the script to it for you. And remember to always use +```Bash +git commit -s +``` +to have git add your Signed-off-by: automatically. + +When you write your commit message, please keep the following two hints in mind: + +* If anyone involved in coreboot reads your comment in a year or so, she or he + shall still be able to understand what your commit is about, without the need + to analyze the code. +* Double-check that you are really committing what you think you are, e.g. by + typing the following in the top-level coreboot directory: +```Bash +git show +``` + [ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergea… [Developer's Certificate of Origin 1.1]: https://developercertificate.org/ [Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/ [this LKML thread]: https://lkml.org/lkml/2004/5/23/10 [SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes +[coreboot's bug tracker]: https://ticket.coreboot.org/ -- To view, visit https://review.coreboot.org/c/coreboot/+/85915?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cd2b13da6fe59697d677c7350d73eda5d486544 Gerrit-Change-Number: 85915 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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[XL] Change in coreboot[main]: mb/starlabs/starbook: Add AlderLake-N variant
by Sean Rhodes (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Matt DeVillier. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85714?usp=email to look at the new patch set (#10). Change subject: mb/starlabs/starbook: Add AlderLake-N variant ...................................................................... mb/starlabs/starbook: Add AlderLake-N variant Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/starbook_adl_n.md M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/Kconfig.name A src/mainboard/starlabs/starbook/variants/adl_n/Makefile.mk A src/mainboard/starlabs/starbook/variants/adl_n/board.fmd A src/mainboard/starlabs/starbook/variants/adl_n/data.vbt A src/mainboard/starlabs/starbook/variants/adl_n/devicetree.cb A src/mainboard/starlabs/starbook/variants/adl_n/devtree.c A src/mainboard/starlabs/starbook/variants/adl_n/gpio.c A src/mainboard/starlabs/starbook/variants/adl_n/hda_verb.c A src/mainboard/starlabs/starbook/variants/adl_n/ramstage.c A src/mainboard/starlabs/starbook/variants/adl_n/romstage.c A src/mainboard/starlabs/starbook/variants/adl_n/vboot.fmd 14 files changed, 1,120 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/85714/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id45e31b61046748a57c8104081f689057621bb04 Gerrit-Change-Number: 85714 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel
by Yu-Ping Wu (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85890?usp=email ) Change subject: mb/google/corsola/var/wyrdeer: Add STA_2082109QFH040022_50E MIPI panel ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85890?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64b907da8ff4e88b9290132033b9300d0b9488cb Gerrit-Change-Number: 85890 Gerrit-PatchSet: 4 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 08:50:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/mipi: Add support for STA_2082109QFH040022_50E panel
by Yu-Ping Wu (Code Review) 09 Jan '25

09 Jan '25

Attention is currently required from: Xinxiong Xu, Yang Wu. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/85889?usp=email ) Change subject: drivers/mipi: Add support for STA_2082109QFH040022_50E panel ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I131e179b7c4420e2038ec4023f9b2f505fc6c088 Gerrit-Change-Number: 85889 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 09 Jan 2025 08:49:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/starlabs/*: Add a CMOS option to disable the GNA
by Sean Rhodes (Code Review) 09 Jan '25

09 Jan '25

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85703?usp=email ) Change subject: mb/starlabs/*: Add a CMOS option to disable the GNA ...................................................................... mb/starlabs/*: Add a CMOS option to disable the GNA Add an option, which defaults to disabled, to control whether the GNA (Gaussian Neural Accelerator) is enabled. This is a device that designed to handle AI tasks. Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85703 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/starlabs/byte_adl/cmos.default M src/mainboard/starlabs/byte_adl/cmos.layout M src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout M src/mainboard/starlabs/starbook/variants/adl/devtree.c M src/mainboard/starlabs/starbook/variants/rpl/devtree.c M src/mainboard/starlabs/starbook/variants/tgl/devtree.c M src/mainboard/starlabs/starfighter/cmos.default M src/mainboard/starlabs/starfighter/cmos.layout M src/mainboard/starlabs/starfighter/variants/rpl/devtree.c M src/mainboard/starlabs/starlite_adl/cmos.default M src/mainboard/starlabs/starlite_adl/cmos.layout M src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c 14 files changed, 39 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/starlabs/byte_adl/cmos.default b/src/mainboard/starlabs/byte_adl/cmos.default index 43a1394..619729f 100644 --- a/src/mainboard/starlabs/byte_adl/cmos.default +++ b/src/mainboard/starlabs/byte_adl/cmos.default @@ -11,3 +11,4 @@ # Devices wireless=Enable webcam=Enable +gna=Disable diff --git a/src/mainboard/starlabs/byte_adl/cmos.layout b/src/mainboard/starlabs/byte_adl/cmos.layout index 0b4984d..d780f6a 100644 --- a/src/mainboard/starlabs/byte_adl/cmos.layout +++ b/src/mainboard/starlabs/byte_adl/cmos.layout @@ -27,6 +27,7 @@ # coreboot config options: Devices 504 1 e 1 wireless +512 1 e 1 gna # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c index 88e8f3a..d762e75 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/devtree.c @@ -20,6 +20,7 @@ &cfg->power_limits_config[ADL_N_041_6W_CORE]; struct device *nic_dev = pcidev_on_root(0x14, 3); + struct device *gna_dev = pcidev_on_root(0x08, 0); uint8_t performance_scale = 100; @@ -53,4 +54,8 @@ cfg->usb2_ports[9].enable = 0; nic_dev->enabled = 0; } + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; } diff --git a/src/mainboard/starlabs/starbook/cmos.default b/src/mainboard/starlabs/starbook/cmos.default index 8cb7190..5959948 100644 --- a/src/mainboard/starlabs/starbook/cmos.default +++ b/src/mainboard/starlabs/starbook/cmos.default @@ -18,6 +18,7 @@ fingerprint_reader=Enable card_reader=Enable lid_switch=Enable +gna=Disable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/starbook/cmos.layout b/src/mainboard/starlabs/starbook/cmos.layout index 55b1629..1f8f247 100644 --- a/src/mainboard/starlabs/starbook/cmos.layout +++ b/src/mainboard/starlabs/starbook/cmos.layout @@ -35,6 +35,7 @@ 542 1 e 1 fingerprint_reader 550 1 e 1 card_reader 558 1 e 1 lid_switch +566 1 e 1 gna # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/starbook/variants/adl/devtree.c b/src/mainboard/starlabs/starbook/variants/adl/devtree.c index b83f6ad..c563d2d 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/adl/devtree.c @@ -22,6 +22,8 @@ struct soc_power_limits_config *soc_conf_12core = &cfg->power_limits_config[ADL_P_682_28W_CORE]; + struct device *gna_dev = pcidev_on_root(0x08, 0); + uint8_t performance_scale = 100; /* Set PL4 to 1.0C */ @@ -69,4 +71,8 @@ /* Enable/Disable Card Reader based on CMOS Settings */ if (get_uint_option("card_reader", 1) == 0) cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; } diff --git a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c index 279f4cf..a8ebcde 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/devtree.c @@ -24,6 +24,7 @@ struct device *tbt_pci_dev = pcidev_on_root(0x07, 0); struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); + struct device *gna_dev = pcidev_on_root(0x08, 0); uint8_t performance_scale = 100; @@ -78,4 +79,8 @@ tbt_pci_dev->enabled = 0; tbt_dma_dev->enabled = 0; } + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; } diff --git a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c index 6df6900..6b7d423 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/devtree.c @@ -22,6 +22,7 @@ struct device *nic_dev = pcidev_on_root(0x14, 3); struct device *tbt_pci_dev = pcidev_on_root(0x07, 0); struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); + struct device *gna_dev = pcidev_on_root(0x08, 0); uint8_t performance_scale = 100; @@ -73,4 +74,8 @@ tbt_pci_dev->enabled = 0; tbt_dma_dev->enabled = 0; } + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; } diff --git a/src/mainboard/starlabs/starfighter/cmos.default b/src/mainboard/starlabs/starfighter/cmos.default index a47d3be..b2f49a5 100644 --- a/src/mainboard/starlabs/starfighter/cmos.default +++ b/src/mainboard/starlabs/starfighter/cmos.default @@ -14,6 +14,7 @@ microphone=Enable pci_hot_plug=Disable lid_switch=Enable +gna=Disable # EC kbl_timeout=30 seconds fn_ctrl_swap=Disable diff --git a/src/mainboard/starlabs/starfighter/cmos.layout b/src/mainboard/starlabs/starfighter/cmos.layout index 27e450d..b161fed 100644 --- a/src/mainboard/starlabs/starfighter/cmos.layout +++ b/src/mainboard/starlabs/starfighter/cmos.layout @@ -31,6 +31,7 @@ 512 1 e 1 webcam 520 1 e 1 microphone 528 1 e 1 lid_switch +536 1 e 1 gna # coreboot config options: EC 600 3 e 4 kbl_timeout diff --git a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c index d4abe940..c9b576a 100644 --- a/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c +++ b/src/mainboard/starlabs/starfighter/variants/rpl/devtree.c @@ -25,6 +25,7 @@ struct device *tbt_pci_dev_0 = pcidev_on_root(0x07, 0); struct device *tbt_pci_dev_1 = pcidev_on_root(0x07, 0); struct device *tbt_dma_dev = pcidev_on_root(0x0d, 2); + struct device *gna_dev = pcidev_on_root(0x08, 0); uint8_t performance_scale = 100; @@ -72,4 +73,8 @@ tbt_pci_dev_1->enabled = 0; tbt_dma_dev->enabled = 0; } + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; } diff --git a/src/mainboard/starlabs/starlite_adl/cmos.default b/src/mainboard/starlabs/starlite_adl/cmos.default index d3c3f80..2a772fc 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.default +++ b/src/mainboard/starlabs/starlite_adl/cmos.default @@ -16,5 +16,6 @@ microphone=Enable lid_switch=Disable power_led=Normal +gna=Disable # EC charging_speed=0.5C diff --git a/src/mainboard/starlabs/starlite_adl/cmos.layout b/src/mainboard/starlabs/starlite_adl/cmos.layout index 909d7655..60441e0 100644 --- a/src/mainboard/starlabs/starlite_adl/cmos.layout +++ b/src/mainboard/starlabs/starlite_adl/cmos.layout @@ -33,6 +33,7 @@ 528 1 e 1 microphone 536 1 e 1 lid_switch 542 1 e 9 power_led +550 1 e 1 gna # coreboot config options: EC 600 2 e 6 max_charge diff --git a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c index dca182c..4ace9b5 100644 --- a/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c +++ b/src/mainboard/starlabs/starlite_adl/variants/mk_v/devtree.c @@ -22,6 +22,7 @@ struct device *nic_dev = pcidev_on_root(0x14, 3); struct device *touchscreen_dev = pcidev_on_root(0x15, 2); struct device *accelerometer_dev = pcidev_on_root(0x15, 0); + struct device *gna_dev = pcidev_on_root(0x08, 0); uint8_t performance_scale = 100; @@ -71,4 +72,8 @@ /* Enable/Disable Accelerometer based on CMOS settings */ if (get_uint_option("accelerometer", 1) == 0) accelerometer_dev->enabled = 0; + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 0) == 0) + gna_dev->enabled = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99f015cf1b5e21e8b524c4aa9bd3e94f86908ca1 Gerrit-Change-Number: 85703 Gerrit-PatchSet: 13 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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