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Change subject: soc/amd/common/acpi: Add SPI flash controller
......................................................................
Patch Set 5:
(1 comment)
File src/soc/amd/common/acpi/spi.asl:
https://review.coreboot.org/c/coreboot/+/84918/comment/5c5c9c47_ce8ddb7c?us… :
PS5, Line 21: ASCE
different values get written to this field from the ASSC method when the driver acquires the bus vs when it releases the bus resulting in different spi chip select pins being used; since the spi flash will always use the same chip select pin, this likely breaks functionality in some case; not sure though which exact case
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Change subject: drivers/amd/opensil: Add openSIL timepoint calls
......................................................................
Patch Set 8: Code-Review+2
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Change subject: mb/amd/crater: Add Crater mainboard support for Renoir/Cezanne SOC
......................................................................
Patch Set 8:
(18 comments)
File src/mainboard/amd/crater/Kconfig:
https://review.coreboot.org/c/coreboot/+/85749/comment/24ad4303_7c02d175?us… :
PS8, Line 33: if BOARD_AMD_CRATER_RENOIR
this if is redundant, since this config option is already inside a "if BOARD_AMD_CRATER_RENOIR" block. same for the 2 config options below
https://review.coreboot.org/c/coreboot/+/85749/comment/15e6fe79_6bbf5204?us… :
PS8, Line 61: default "3rdparty/blobs/mainboard/amd/crater/EcSig_Crater.bin"
since this file isn't available in the public blobs repo, i'd say that we should have this in the .config used in the build instead of here in the kconfig
https://review.coreboot.org/c/coreboot/+/85749/comment/614f27a5_06046f2d?us… :
PS8, Line 87:
there should only be one empty line
https://review.coreboot.org/c/coreboot/+/85749/comment/47edcca6_ed1185c6?us… :
PS8, Line 105: choice
: prompt "I2C Speed Selection"
: default SELECT_400KHz
: help
: Select Different speeds of I2C 400KHz / 1 MHz
:
: config SELECT_400KHz
: bool "400KHz"
:
: config SELECT_1MHz
: bool "1MHz"
:
: endchoice
not needed, since the i2c speed can and should be configured in the devicetree
File src/mainboard/amd/crater/chromeos.c:
https://review.coreboot.org/c/coreboot/+/85749/comment/d8f3cd19_6eaf0658?us… :
PS8, Line 17: Birman
Crater
File src/mainboard/amd/crater/chromeos_renoir.fmd:
PS8:
not sure if the PSP_NVRAM and PSP_RPMC_NVRAM fmpa sections would easily fit into the fmap. if so, it might be good to add those; i'm fine with that being looked into in some follow-up patch
File src/mainboard/amd/crater/devicetree_renoir.cb:
https://review.coreboot.org/c/coreboot/+/85749/comment/309ebf86_9f2ab003?us… :
PS8, Line 3:
only one empty line
https://review.coreboot.org/c/coreboot/+/85749/comment/135b59cc_d9f03355?us… :
PS8, Line 43: register "gpp_clk_config[0]" = "GPP_CLK_ON"
: register "gpp_clk_config[1]" = "GPP_CLK_ON"
: register "gpp_clk_config[2]" = "GPP_CLK_ON"
: register "gpp_clk_config[3]" = "GPP_CLK_ON"
: register "gpp_clk_config[4]" = "GPP_CLK_ON"
: register "gpp_clk_config[5]" = "GPP_CLK_ON"
: register "gpp_clk_config[6]" = "GPP_CLK_ON"
haven't checked with the schematic, but some of those probably aren't correct. feel free to keep it as it is for now and revisit this later, since this would be mainly an optimization to lower the power consumption
File src/mainboard/amd/crater/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/85749/comment/e812dac4_fac03143?us… :
PS8, Line 13:
should be tab not spaces
https://review.coreboot.org/c/coreboot/+/85749/comment/091e1bcc_fe6ea363?us… :
PS8, Line 70: };
i'd add an empty line between the array and the function here
File src/mainboard/amd/crater/ec.h:
https://review.coreboot.org/c/coreboot/+/85749/comment/3b45450c_1c235810?us… :
PS8, Line 7: void crater_boardrevision(void);
i'd add an empty line between the last function and the #endif
File src/mainboard/amd/crater/ec.c:
https://review.coreboot.org/c/coreboot/+/85749/comment/c2b17876_3f9f551b?us… :
PS8, Line 156: void crater_boardrevision(void)
hmm, i wonder if it would be cleaner if this file provides a function to get the board revision and have the revision-specific soc gpio configuration done in the mainboard code that configures the soc gpios
File src/mainboard/amd/crater/gpio.c:
PS8:
this is probably missing some gpios
https://review.coreboot.org/c/coreboot/+/85749/comment/5be01867_8a458178?us… :
PS8, Line 16:
tab
File src/mainboard/amd/crater/port_descriptors_renoir.c:
https://review.coreboot.org/c/coreboot/+/85749/comment/a6e9af65_d2961bca?us… :
PS8, Line 96: ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA);
: BoardRev = ec_read(ECRAM_BOARDID_OFFSET + 0x3);
would be good to have a function in the mainboard's ec code for this
https://review.coreboot.org/c/coreboot/+/85749/comment/0c481978_4bdf38a5?us… :
PS8, Line 115: void __weak mainboard_fsp_mainboard_params_init(FSP_M_CONFIG *m_config)
: {
:
: }
i don't see this function being needed or called, so it can likely be removed. same for the prototype in line 12
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/85749/comment/41fc7880_13d86a45?us… :
PS8, Line 112: bool acp_i2s_use_external_48mhz_osc;
this and the corresponding change in the cezanne soc code should be done in a separate patch before adding the mainboard
File src/soc/amd/cezanne/include/soc/gpio.h:
PS8:
this change should also be split out into a separate patch, so that the mainboard patch doesn't need to touch any files outside of the mainboard directory
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Change subject: doc/util/ifdtool: Update instructions
......................................................................
Patch Set 2: Code-Review+2
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Change subject: lib/{fit,fit_payload}.c: Enhance support for FIT images
......................................................................
Patch Set 11:
(6 comments)
File payloads/Kconfig:
https://review.coreboot.org/c/coreboot/+/84796/comment/16d555a5_a7681982?us… :
PS11, Line 33: depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM || ARCH_X86
Actually, does this line still make sense at all? You aren't adding any x86-specific code in this patch anymore, and the firmware loading support would work on all architectures (e.g. also PPC64 or some new one we might add in the future). I'd say just take out the architecture dependency completely here (and below).
File src/lib/fit.c:
https://review.coreboot.org/c/coreboot/+/84796/comment/eaaed53f_50b080df?us… :
PS11, Line 512: strcmp(config->name, default_config_name)
This can crash if `default_config_name` remains `NULL` because there is no `default` prop. I'd recommend writing this like I suggested in https://review.coreboot.org/c/coreboot/+/84796/6..11/src/lib/fit.c#b509
File src/lib/fit_payload.c:
https://review.coreboot.org/c/coreboot/+/84796/comment/6783034d_dfb7973d?us… :
PS9, Line 22: printk(BIOS_CRIT, "WEAK: Generic code called to load a FIT kernel!\n");
> Done
String doesn't seem to be changed in latest patch set yet?
https://review.coreboot.org/c/coreboot/+/84796/comment/27d7d293_e683846a?us… :
PS9, Line 29: printk(BIOS_ERR, "WEAK: %s:%s() called to add %s to FDT\n", __FILE__, __func__, name);
> Oh, I see what happened. I was looking at the PDF, where the introduction is "chapter 4." I'm referring to the introduction, subsection .1, the second paragraph.
Okay, but that doesn't really mean much. I think it is true that e.g. U-Boot uses FIT images to package and load later components in its boot process, but that doesn't make these components universal in a way that coreboot could use them as well. They are specific to U-Boot both in what they're actually doing and in their calling convention. Just because two code bases may both be using the FIT image container doesn't mean what they're putting in that container could be compatible.
So I don't think it makes sense to try to write any coreboot code that just allows booting "any" kind of FIT image — that is impossible. A FIT image must always come with a defined calling convention (which tells you which images to load and how to enter them). There may be some common practices that all those calling conventions tend to follow but that doesn't mean you could properly boot an image without them.
Right now AFAIK there are only two well-defined, portable FIT image calling conventions, Linux kernel and UPL. So I'd say let's focus on those and not worry about any others until they're officially specced and someone has a need for them in coreboot. That means that whenever `config->firmware` is set, you know you're in the UPL calling convention and you can just run whatever code you need to run to e.g. describe secondaries in the FDT in whatever way UPL wants to... you don't need to build an extensible interface where other non-UPL code paths could hook in yet.
(Also, I just noticed another problem with the implementation you used to have here: you aren't actually allowed to add DT nodes and properties at this point because you had already called `dt_flat_size()` to determine the total FDT size to place in memory beforehand. You can only overwrite properties that you know are already there with the same data size (or less), or you need to come up with some heuristic to calculate how much space you need to reserve extra in advance to ensure there'll be enough space for what you're planning to add later.)
File src/lib/fit_payload.c:
https://review.coreboot.org/c/coreboot/+/84796/comment/70dc51c6_b6a54e92?us… :
PS11, Line 181: /* Collect info for fit_linux_arch_quirks */
This is totally off-topic to your patch (already a bug in the existing code), but I think there should be a
```
if (config->ramdisk)
fit_add_ramdisk(dt, 0, 0);
```
here before the `dt_flat_size()`. Otherwise, it's possible that adding the ramdisk props below will grow the FDT beyond what was placed by the arch code. I think the current code was written with the assumption that FIT images would always have those props existing (with bogus values) already, but it's bad to blindly assume that, it would be better to just make sure.
https://review.coreboot.org/c/coreboot/+/84796/comment/451b194e_cfb65325?us… :
PS11, Line 203: if (config->ramdisk &&
Can merge this into previous `if` now.
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Change subject: commonlib/device_tree.c: Add a function that reads FDT ints
......................................................................
Patch Set 6:
(1 comment)
File src/commonlib/device_tree.c:
https://review.coreboot.org/c/coreboot/+/85643/comment/bcf9f91d_389d1166?us… :
PS6, Line 267: printk(BIOS_DEBUG, "FDT integer property of size %u @%p is %u cells\n", prop->size, prop->data, cells);
I don't think we'll want to print this every time, it's just gonna be spam.
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Hello Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu, Vasiliy Khoruzhick, build bot (Jenkins), yuchi.chen(a)intel.com,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Add fix for DPR silicon bug
......................................................................
soc/intel/xeon_sp: Add fix for DPR silicon bug
On first batch of Intel Xeon-SP 10nm CPU the DPR register is affected
by a silicon bug, where the TOP bits read as 0, which isn't possible
according to the EDS. Currently the code also assumes that it's never
zero and calculates the DPR size using the assigned address. By using
0 as TOP address it overflows and breaks boot due to an overly large
MMIO window.
On previous CPUs and newer CPUs the assumption is still correct and
the DPR TOP bits never read as 0.
Add a check for the silicon bug and use TSEG base like it's already
done on snowridge, which is also a 10nm Xeon CPU affected by the
same bug.
Fixes negative size being calculated for DPR.
Change-Id: Ia090013721053ae85001a3e7d47ad2b1ec9a3203
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/snowridge/systemagent.c
M src/soc/intel/xeon_sp/uncore.c
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85829/3
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