coreboot-gerrit September 2024

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[S] Change in coreboot[main]: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84115?usp=email ) Change subject: soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c ...................................................................... soc/mediatek/common: Move mtk_pcie_reset to common/pcie.c mtk_pcie_reset can be shared with MT8196. So move it to common/pcie.c. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84115 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/Makefile.mk M src/soc/mediatek/mt8195/include/soc/pcie.h M src/soc/mediatek/mt8195/pcie.c 5 files changed, 15 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Jianjun Wang: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index 0f02ab7..c34bc4e 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -22,5 +22,6 @@ void mtk_pcie_domain_read_resources(struct device *dev); void mtk_pcie_domain_set_resources(struct device *dev); void mtk_pcie_domain_enable(struct device *dev); +void mtk_pcie_reset(uintptr_t base_reg, bool enable); #endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index 39714e1..e796dc1 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -247,6 +247,16 @@ pci_domain_set_resources(dev); } +void mtk_pcie_reset(uintptr_t base_reg, bool enable) +{ + uint32_t flags = PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; + + if (enable) + setbits32p(base_reg + PCIE_RST_CTRL_REG, flags); + else + clrbits32p(base_reg + PCIE_RST_CTRL_REG, flags); +} + enum cb_err fill_lb_pcie(struct lb_pcie *pcie) { if (!pci_root_bus()) @@ -291,7 +301,7 @@ printk(BIOS_WARNING, "%s: PCIe early init data not found, sleeping 100ms\n", __func__); - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(conf->base, true); } else { printk(BIOS_WARNING, "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", @@ -302,7 +312,7 @@ } /* De-assert reset signals */ - mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); + mtk_pcie_reset(conf->base, false); if (!retry(100, (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 3446144..a37f715 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -13,7 +13,7 @@ bootblock-y += ../common/early_init.c bootblock-y += ../common/eint_event.c bootblock-y += ../common/mmu_operations.c -bootblock-$(CONFIG_PCI) += pcie.c +bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h index 117f4cc..75c52c1 100644 --- a/src/soc/mediatek/mt8195/include/soc/pcie.h +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -6,7 +6,6 @@ #include <soc/pcie_common.h> #include <types.h> -void mtk_pcie_reset(uintptr_t reg, bool enable); void mtk_pcie_pre_init(void); bool mainboard_needs_pcie_init(void); diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index eb7ad87..2676207 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -9,11 +9,6 @@ #include <soc/pcie_common.h> #define PCIE_REG_BASE_PORT0 0x112f0000 -#define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) -#define PCIE_MAC_RSTB BIT(0) -#define PCIE_PHY_RSTB BIT(1) -#define PCIE_BRG_RSTB BIT(2) -#define PCIE_PE_RSTB BIT(3) struct pad_func { gpio_t gpio; @@ -46,28 +41,12 @@ } } -void mtk_pcie_reset(uintptr_t reg, bool enable) -{ - uint32_t val; - - val = read32p(reg); - - if (enable) - val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB; - else - val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | - PCIE_PE_RSTB); - - write32p(reg, val); -} - void mtk_pcie_pre_init(void) { mtk_pcie_set_pinmux(0); /* Assert all reset signals at early stage */ - mtk_pcie_reset(PCIE_RST_CTRL_REG, true); + mtk_pcie_reset(PCIE_REG_BASE_PORT0, true); early_init_save_time(EARLY_INIT_PCIE); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib540cf9cc568206a1e78306624f4df7c5631c128 Gerrit-Change-Number: 84115 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/mediatek/common/pcie: Use clr/setbits32p
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84114?usp=email ) Change subject: soc/mediatek/common/pcie: Use clr/setbits32p ...................................................................... soc/mediatek/common/pcie: Use clr/setbits32p Use clr/setbits32p to make code cleaner. BUG=none TEST=emerge-cherry coreboot Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84114 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 4 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Jianjun Wang: Looks good to me, approved diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c07cc4f..39714e1 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -266,20 +266,14 @@ uint32_t val; /* Set as RC mode */ - val = read32p(conf->base + PCIE_SETTING_REG); - val |= PCIE_RC_MODE; - write32p(conf->base + PCIE_SETTING_REG, val); + setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE); /* Set class code */ - val = read32p(conf->base + PCIE_PCI_IDS_1); - val &= ~GENMASK(31, 8); - val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); - write32p(conf->base + PCIE_PCI_IDS_1, val); + clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8), + PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); /* Mask all INTx interrupts */ - val = read32p(conf->base + PCIE_INT_ENABLE_REG); - val &= ~PCIE_INTX_ENABLE; - write32p(conf->base + PCIE_INT_ENABLE_REG, val); + clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/84114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id99d5aafdf4d687dbe3a0bef29b148537cf58dd8 Gerrit-Change-Number: 84114 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/common/pcie: Add DEVTREE_CONST qualifier
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84113?usp=email ) Change subject: soc/mediatek/common/pcie: Add DEVTREE_CONST qualifier ...................................................................... soc/mediatek/common/pcie: Add DEVTREE_CONST qualifier Currently pcie.c is built into ramstage only, where DEVTREE_CONST is an empty macro, so there's no problem with that. However, if we would like to include that file in pre-ramstage, then DEVTREE_CONST would be 'const', leading to the following build error: ``` src/soc/mediatek/common/pcie.c:104:26: error: assignment discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] 104 | root_dev = pcidev_path_on_root(devfn); | ^ ``` BUG=none TEST=emerge-cherry coreboot Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84113 Reviewed-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Jianjun Wang: Looks good to me, approved diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index ce9055a..c07cc4f 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -96,7 +96,7 @@ static uintptr_t mtk_pcie_get_controller_base(pci_devfn_t devfn) { - struct device *root_dev; + DEVTREE_CONST struct device *root_dev; const mtk_soc_config_t *config; static uintptr_t base = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/84113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7c95424019ec0dca50bbc6be7f81b6180d06d6e Gerrit-Change-Number: 84113 Gerrit-PatchSet: 4 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox: Remove ACPI Power Resource for Bluetooth device
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84135?usp=email ) Change subject: mb/google/brox: Remove ACPI Power Resource for Bluetooth device ...................................................................... mb/google/brox: Remove ACPI Power Resource for Bluetooth device Bluetooth driver in kernel requires reset-gpio in current resource settings (_CRS) and device specific data (_DSD) ACPI objects. Hence remove ACPI Power Resource for Bluetooth device so that the concerned ACPI objects get populated. BUG=b:362817900 TEST=Build Brox Firmware image and boot to OS. Ensure that the _CRS and _DSP ACPI objects are filled in the SSDT with the required data. Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x004D } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "reset-gpio", Package (0x04) { \_SB.PCI0.XHCI.RHUB.HS10, Zero, Zero, One } } } }) Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84135 Reviewed-by: Bob Moragues <moragues(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/lotso/overridetree.cb 3 files changed, 0 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Bob Moragues: Looks good to me, but someone else must approve Ren Kuo: Looks good to me, approved diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 37c4e01..f2342f0 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -247,7 +247,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index bd7fca0..d1fbb8b 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -203,7 +203,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb index e81848d..0f87889 100644 --- a/src/mainboard/google/brox/variants/lotso/overridetree.cb +++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb @@ -302,7 +302,6 @@ chip drivers/usb/acpi register "desc" = ""USB2 Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" - register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" device ref usb2_port10 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/84135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e679aa3f4181e7963ac53d0847b1512959b3a7 Gerrit-Change-Number: 84135 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/brox/jubilant: Update dptf settings
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84123?usp=email ) Change subject: mb/google/brox/jubilant: Update dptf settings ...................................................................... mb/google/brox/jubilant: Update dptf settings Update dptf settings from thermal design: 1) Remove fan control and active policy, since fan is controlled by EC. 2) Modify TSRs to 0:DRAM, 1:SOC, 2:Charger 3) Update Pl2 min&max values BUG=None TEST= Build jubilant firmware Generate and check ACPI SSDT.dsl $ cat /sys/firmware/acpi/tables/SSDT > SSDT $ iasl -d SSDT Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84123 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues(a)google.com> --- M src/mainboard/google/brox/variants/jubilant/overridetree.cb 1 file changed, 17 insertions(+), 73 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Kenneth Chan: Looks good to me, approved Bob Moragues: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 6d7c3f8..bd7fca0 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -45,51 +45,12 @@ register "options.tsr[1].desc" = ""Soc"" register "options.tsr[2].desc" = ""Charger"" - ## Active Policy - register "policies.active" = "{ - [0] = { - .target = DPTF_CPU, - .thresholds = { - TEMP_PCT(95, 90), - TEMP_PCT(92, 80), - TEMP_PCT(89, 60), - TEMP_PCT(85, 40), - TEMP_PCT(80, 30), - } - }, - [1] = { - .target = DPTF_TEMP_SENSOR_0, - .thresholds = { - TEMP_PCT(54, 95), - TEMP_PCT(52, 90), - TEMP_PCT(50, 80), - TEMP_PCT(48, 50), - TEMP_PCT(46, 30), - TEMP_PCT(44, 25), - TEMP_PCT(42, 20), - TEMP_PCT(40, 15), - } - }, - [2] = { - .target = DPTF_TEMP_SENSOR_1, - .thresholds = { - TEMP_PCT(54, 95), - TEMP_PCT(52, 90), - TEMP_PCT(50, 80), - TEMP_PCT(48, 50), - TEMP_PCT(46, 30), - TEMP_PCT(44, 25), - TEMP_PCT(42, 20), - TEMP_PCT(40, 15), - } - } - }" - ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000), + [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000), }" ## Critical Policy @@ -97,23 +58,24 @@ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 15000, - .max_power = 18000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200, - }, + .min_power = 15000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, .pl2 = { - .min_power = 55000, - .max_power = 55000, - .time_window_min = 28 * MSECS_PER_SEC, - .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 1000, - } + .min_power = 41000, + .max_power = 41000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } }" ## Charger Performance Control (Control, mA) @@ -124,24 +86,6 @@ [3] = { 8, 500 } }" - ## Fan Performance Control (Percent, Speed, Noise, Power) - register "controls.fan_perf" = "{ - [0] = { 90, 6700, 220, 2200, }, - [1] = { 80, 5800, 180, 1800, }, - [2] = { 70, 5000, 145, 1450, }, - [3] = { 60, 4900, 115, 1150, }, - [4] = { 50, 3838, 90, 900, }, - [5] = { 40, 2904, 55, 550, }, - [6] = { 30, 2337, 30, 300, }, - [7] = { 20, 1608, 15, 150, }, - [8] = { 10, 800, 10, 100, }, - [9] = { 0, 0, 0, 50, } - }" - - ## Fan options - register "options.fan.fine_grained_control" = "1" - register "options.fan.step_size" = "2" - device generic 0 alias dptf_policy on end end end # DTT -- To view, visit https://review.coreboot.org/c/coreboot/+/84123?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d59eedea9fb25565709e118abc1a14b4c2a64e7 Gerrit-Change-Number: 84123 Gerrit-PatchSet: 4 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up microcode from repository
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84125?usp=email ) Change subject: soc/intel/meteorlake: Hook up microcode from repository ...................................................................... soc/intel/meteorlake: Hook up microcode from repository Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84125 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/Makefile.mk 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: Nico Huber: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 3b31e53..79ef3e8 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -37,7 +37,6 @@ select INTEL_GMA_OPREGION_2_1 select INTEL_GMA_VERSION_2 select IOAPIC - select MICROCODE_BLOB_UNDISCLOSED select MP_SERVICES_PPI_V2 select MRC_CACHE_USING_MRC_VERSION select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index 72d1117..495ea5b 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -59,4 +59,8 @@ CPPFLAGS_common += -I$(src)/soc/intel/meteorlake CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include +ifeq ($(CONFIG_SOC_INTEL_METEORLAKE_U_H),y) +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-aa-04 +endif + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/84125?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46021accacbb911d7a7ecfdbb52973a7da78f36e Gerrit-Change-Number: 84125 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: src/include/: Introducing a new BIT_32(x) macro.
by Arthur Heymans (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Ashish Kumar Mishra, Martin Roth, Saurabh Mishra. Arthur Heymans has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include/: Introducing a new BIT_32(x) macro. ...................................................................... Patch Set 7: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 7 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 09:00:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/cwwk/adl/devicetree: enable all USB ports
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83910?usp=email ) Change subject: mb/cwwk/adl/devicetree: enable all USB ports ...................................................................... mb/cwwk/adl/devicetree: enable all USB ports The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on the mainboard and likely also routes one USB2 port to the m.2 E key slot which is typically used for Bluetooth support when an E key m.2 WIFI + Bluetooth card is installed. This is untested, since I only have the cw-al-4l-v2.0 mainboard, but from looking at the documentation of the version 1 and looking at how things are done on the version 2 this should be correct. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/cwwk/adl/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index c4c5e8c..86a31e7 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -6,7 +6,10 @@ register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 0, -- To view, visit https://review.coreboot.org/c/coreboot/+/83910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d Gerrit-Change-Number: 83910 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Brandon Weeks <bweeks(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
by Saurabh Mishra (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N, Subrata Banik. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ...................................................................... Patch Set 75: (1 comment) File src/soc/intel/pantherlake/systemagent.c: https://review.coreboot.org/c/coreboot/+/83798/comment/64cb901e_e58d3b3d?us… : PS71, Line 33: // PCH_PRESERVERD covers: : // TraceHub SW BAR, PMC MBAR, SPI BAR0, SerialIo BAR in ACPI mode : // eSPI LGMR BAR, eSPI2 SEGMR BAR, TraceHub MTB BAR, TraceHub FW BAR : // IOE PMC BAR, Tracehub RTIT BAR (SOC), HECI{1,2,3} BAR0 : // see fsp/ClientOneSiliconPkg/Fru/MtlSoc/Include/PchReservedResources.h > Sure, i have removed the comments. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362 Gerrit-Change-Number: 83798 Gerrit-PatchSet: 75 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 08:53:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: src/include/: Introducing a new BIT_32(x) macro.
by Subrata Banik (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Martin Roth, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/84142?usp=email ) Change subject: src/include/: Introducing a new BIT_32(x) macro. ...................................................................... Patch Set 7: (1 comment) File src/include/types.h: https://review.coreboot.org/c/coreboot/+/84142/comment/0bb74e19_38dea0ec?us… : PS5, Line 27: > > > I have refactored to tackle above error. > > > > > > #ifdef BIT_32 > > > #undef BIT_32 > > > #endif > > > > Overriding other code is not the right approach. Simple use a #ifdef without undef? > > #ifndef https://review.coreboot.org/c/coreboot/+/84142/5..7/src/include/types.h#b24 -- To view, visit https://review.coreboot.org/c/coreboot/+/84142?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I70be1ccba59d25af2ba85a2014232072abf2f87d Gerrit-Change-Number: 84142 Gerrit-PatchSet: 7 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 08:53:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit September 2024