coreboot-gerrit September 2024

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[M] Change in coreboot[main]: drivers/usb/acpi: Add DSM for Intel Bluetooth
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84133?usp=email ) Change subject: drivers/usb/acpi: Add DSM for Intel Bluetooth ...................................................................... drivers/usb/acpi: Add DSM for Intel Bluetooth Add support for creating a DSM Method for Intel Bluetooth that is outlined in Intel's connectivity integrated guide (which has no document number). It supports two GUIDs: Set Tile Activaction (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Tile Activation Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9) BIT(0) Indicates whether the device supports other functions BIT(1) Set Bluetooth reset timing Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84133 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 129 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 9acd382..855a5d7 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -47,6 +47,9 @@ /* Does the device have a power resource? */ bool has_power_resource; + /* Intel Bluetooth */ + bool is_intel_bluetooth; + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; /* Delay to be inserted after device is taken out of reset. */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 569147a..b01c949 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -8,6 +8,129 @@ #include <device/device.h> #include "chip.h" +/* + * Intel Bluetooth DSM + * + * Check Tile Activation (2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9) + * + * Arg2 == 0: Return a package with the following bits set + * BIT(0) Indicates whether the device supports other functions + * BIT(1) Check Tile Activation + * + * Check/Set Reset Delay (aa10f4e0-81ac-4233-abf6-3b2ac50e28d9) + * Arg2 == 0: Return a package with the following bit set + * BIT(0) Indicates whether the device supports other functions + * BIT(1) Check Bluetooth reset timing + * Arg2 == 1: Set the reset delay based on Arg3 + */ + +static void check_reset_delay(void *arg) +{ + acpigen_write_if_lequal_op_int(ARG1_OP, 0); + { + acpigen_write_return_singleton_buffer(0x03); + } + acpigen_write_else(); + { + acpigen_write_return_singleton_buffer(0x00); + } + acpigen_pop_len(); +} + +static void set_reset_delay(void *arg) +{ + acpigen_write_store_op_to_namestr(ARG3_OP, "RDLY"); +} + +static void get_feature_flag(void *arg) +{ + acpigen_write_if_lequal_op_int(ARG1_OP, 0); + { + acpigen_write_return_singleton_buffer(0x03); + } + acpigen_write_else(); + { + acpigen_write_return_singleton_buffer(0x00); + } + acpigen_pop_len(); +} + +void (*uuid_callbacks1[])(void *) = { check_reset_delay, set_reset_delay }; +void (*uuid_callbacks2[])(void *) = { get_feature_flag }; + +static void acpi_device_intel_bt(void) +{ +/* + * Name (RDLY, 0x69) + */ + acpigen_write_name_integer("RDLY", 0x69); + +/* + * Method (_DSM, 4, Serialized) + * { + * If ((Arg0 == ToUUID ("aa10f4e0-81ac-4233-abf6-3b2ac50e28d9"))) + * { + * If ((Arg2 == Zero)) + * { + * If ((Arg1 == Zero)) + * { + * Return (Buffer (One) + * { + * 0x03 + * }) + * } + * Else + * { + * Return (Buffer (One) + * { + * 0x00 + * }) + * } + * } + * If ((Arg2 == One)) + * { + * RDLY = Arg3 + * } + * Return (Zero) + * } + * ElseIf ((Arg0 == ToUUID ("2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9"))) + * { + * If ((Arg2 == Zero)) + * { + * If ((Arg1 == Zero)) + * { + * Return (Buffer (One) + * { + * 0x00 + * }) + * } + * Else + * { + * Return (Buffer (One) + * { + * 0x00 + * }) + * } + * } + * Return (Zero) + * } + * Else + * { + * Return (Buffer (One) + * { + * 0x00 + * }) + * } + * } + */ + struct dsm_uuid uuid_callbacks[] = { + DSM_UUID("aa10f4e0-81ac-4233-abf6-3b2ac50e28d9", uuid_callbacks1, 2, NULL), + DSM_UUID("2d19d3e1-5708-4696-bd5b-2c3dbae2d6a9", uuid_callbacks2, 1, NULL), + }; + + acpigen_write_dsm_uuid_arr(uuid_callbacks, ARRAY_SIZE(uuid_callbacks)); +} + static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { if (cfg->privacy_gpio.pin_count) @@ -107,6 +230,9 @@ acpi_device_add_power_res(&power_res_params); } + if (config->is_intel_bluetooth) + acpi_device_intel_bt(); + acpigen_pop_len(); printk(BIOS_INFO, "%s: %s at %s\n", path, -- To view, visit https://review.coreboot.org/c/coreboot/+/84133?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc18f867604876b27ced2ee4356e47b3aa6b4f74 Gerrit-Change-Number: 84133 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/zork: Ensure eSPI GPIOs programmed w/o vboot
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84148?usp=email ) Change subject: mb/google/zork: Ensure eSPI GPIOs programmed w/o vboot ...................................................................... mb/google/zork: Ensure eSPI GPIOs programmed w/o vboot On the non-vboot boot path, eSPI is configured as part of fch_pre_init(), and we need to ensure that the mainboard sets the eSPI GPIOs properly before the common SoC code performs eSPI init. Use the mb_set_up_early_espi() function to set the eSPI GPIOs at the correct time. TEST=build/boot google/zork (morphius), verify keyboard functional. Change-Id: I03efe6def37a018c3de410523be21bf008174e94 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84148 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/bootblock.c 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index 559ca04d..202b957 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -3,6 +3,16 @@ #include <bootblock_common.h> #include <baseboard/variants.h> #include <acpi/acpi.h> +#include <amdblocks/espi.h> + +void mb_set_up_early_espi(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = variant_espi_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); +} void bootblock_mainboard_early_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/84148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03efe6def37a018c3de410523be21bf008174e94 Gerrit-Change-Number: 84148 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/zork: Ensure early GPIOs programmed w/o vboot
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84147?usp=email ) Change subject: mb/google/zork: Ensure early GPIOs programmed w/o vboot ...................................................................... mb/google/zork: Ensure early GPIOs programmed w/o vboot Now that zork can boot without vboot, ensure that the GPIOs set in verstage are programmed in bootblock on the non-vboot path. The eSPI GPIOs will be set in a subsequent patch using mb_set_up_early_espi() since setting them in bootblock_mainboard_early_init() would be too late given when the SoC eSPI init takes place. TEST=build/boot google/zork (morphius) w/o vboot Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84147 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/google/zork/bootblock.c 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/google/zork/bootblock.c b/src/mainboard/google/zork/bootblock.c index 022a5e0..559ca04d 100644 --- a/src/mainboard/google/zork/bootblock.c +++ b/src/mainboard/google/zork/bootblock.c @@ -9,6 +9,19 @@ size_t num_gpios; const struct soc_amd_gpio *gpios; + /* + * The GPIOs below would normally be programmed in verstage, but + * if we're not using PSP verstage, need to set them up here instead. + */ + if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { + gpios = variant_early_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); + + gpios = variant_tpm_gpio_table(&num_gpios); + gpio_configure_pads(gpios, num_gpios); + + } + gpios = variant_bootblock_gpio_table(&num_gpios, acpi_get_sleep_type()); gpio_configure_pads(gpios, num_gpios); -- To view, visit https://review.coreboot.org/c/coreboot/+/84147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0bb49678b2d913c447d5bc761a6f0e00fca6334f Gerrit-Change-Number: 84147 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/teliks: Add fw_config fields for rtl8852be
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84138?usp=email ) Change subject: mb/google/nissa/var/teliks: Add fw_config fields for rtl8852be ...................................................................... mb/google/nissa/var/teliks: Add fw_config fields for rtl8852be Add a new fw config field for wifi category as WIFI_6_8852, which is PCIe based. Also, enable WIFI_6_8852 for existing PCIe based wifi port as well as bluetooth port. BUG=b:356434907 BRANCH=NONE TEST=Verified Wifi6 module detection Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84138 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/teliks/overridetree.cb M src/mainboard/google/brya/variants/teliks/variant.c 2 files changed, 8 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Qinghong Zeng: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/teliks/overridetree.cb b/src/mainboard/google/brya/variants/teliks/overridetree.cb index 2f4534f..d2603f1 100644 --- a/src/mainboard/google/brya/variants/teliks/overridetree.cb +++ b/src/mainboard/google/brya/variants/teliks/overridetree.cb @@ -1,8 +1,9 @@ fw_config field WIFI 8 9 option UNKNOWN 0 - option WIFI_6 1 + option WIFI_6_7921 1 option WIFI_6E 2 + option WIFI_6_8852 3 end field CAMERA 10 11 option UF_720P_WF 0 @@ -406,7 +407,8 @@ register "wake" = "GPE0_DW1_03" register "add_acpi_dma_property" = "true" device pci 00.0 on - probe WIFI WIFI_6 + probe WIFI WIFI_6_7921 + probe WIFI WIFI_6_8852 end end end @@ -511,7 +513,8 @@ register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port8 on - probe WIFI WIFI_6 + probe WIFI WIFI_6_7921 + probe WIFI WIFI_6_8852 end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/teliks/variant.c b/src/mainboard/google/brya/variants/teliks/variant.c index 3f7cfd6..7e0f02d 100644 --- a/src/mainboard/google/brya/variants/teliks/variant.c +++ b/src/mainboard/google/brya/variants/teliks/variant.c @@ -35,7 +35,8 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6))) { + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6_7921)) + || fw_config_probe(FW_CONFIG(WIFI, WIFI_6_8852))) { printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); gpio_padbased_override(padbased_table, wifi_pcie_enable_pad, ARRAY_SIZE(wifi_pcie_enable_pad)); -- To view, visit https://review.coreboot.org/c/coreboot/+/84138?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib6ba641c23cce7f1253022c9bb78b986b323bcaa Gerrit-Change-Number: 84138 Gerrit-PatchSet: 3 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/teliks: Force audio mute to avoid screen flick
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84137?usp=email ) Change subject: mb/google/nissa/var/teliks: Force audio mute to avoid screen flick ...................................................................... mb/google/nissa/var/teliks: Force audio mute to avoid screen flick Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, it is because it inserts 12 blank frames if it receives the unmute in VB-ID. Always override the mute in VB-ID to avoid Tcon EC detected the audiomute_flag change. BUG=b:360243615 BRANCH=firmware-nissa-15217.B TEST:Verfied on Teliks and cannot reproduce the issue Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84137 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/teliks/variant.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Qinghong Zeng: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/teliks/variant.c b/src/mainboard/google/brya/variants/teliks/variant.c index 7cc4af8..3f7cfd6 100644 --- a/src/mainboard/google/brya/variants/teliks/variant.c +++ b/src/mainboard/google/brya/variants/teliks/variant.c @@ -5,6 +5,11 @@ #include <fw_config.h> #include <sar.h> #include <soc/gpio_soc_defs.h> +#include <intelblocks/graphics.h> + +/* Per-pipe DDI Function Control 2 */ +#define TRANS_DDI_FUNC_CTL2_A 0x60404 +#define TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS (3 << 6) const char *get_wifi_sar_cbfs_filename(void) { @@ -36,3 +41,16 @@ ARRAY_SIZE(wifi_pcie_enable_pad)); } } + +void variant_finalize(void) +{ + /* + * Panel CSOT MNB601LS1-3 will flicker once during enter Chrome login screen, + * it is because it inserts 12 blank frames if it receives the unmute in VB-ID. + * + * Always override the mute in VB-ID to avoid Tcon EC detected the + * audiomute_flag change. + */ + graphics_gtt_rmw(TRANS_DDI_FUNC_CTL2_A, ~TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS, + TRANS_DDI_AUDIO_MUTE_OVERRIDE_BITS_FIELDS); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iff488f6844c717ef24069c7176e7b8dfb07d8abc Gerrit-Change-Number: 84137 Gerrit-PatchSet: 3 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: include/device/pci_def.h: Add PCIe SRIOV definitions
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Jérémy Compostella, yuchi.chen(a)intel.com. Felix Held has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83319?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: include/device/pci_def.h: Add PCIe SRIOV definitions ...................................................................... Patch Set 15: (1 comment) File src/include/device/pci_def.h: https://review.coreboot.org/c/coreboot/+/83319/comment/44a68b3b_36f4cdc1?us… : PS15, Line 587: #define PCIE_EXT_CAP_SRIOV_TOTAL_VFS 0x0e in the other definitions in this file, the value is tab-aligned; would be good to do that here too -- To view, visit https://review.coreboot.org/c/coreboot/+/83319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4bf76b0e3b20e3d04e8264c6530ab4abb95a013 Gerrit-Change-Number: 83319 Gerrit-PatchSet: 15 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 09:08:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/systemagent: read sa resources only from domain 0
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84109?usp=email ) Change subject: soc/intel/common/systemagent: read sa resources only from domain 0 ...................................................................... soc/intel/common/systemagent: read sa resources only from domain 0 Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84109 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index bca442b..e8d7432 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -273,6 +273,12 @@ { int index = 0; + /** + * If SoC has multiple PCIe domains, only reading resources from the first one. + */ + if (!is_dev_on_domain0(dev)) + return; + /* Read standard PCI resources. */ pci_dev_read_resources(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/84109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida4461de6275bdd314f5cba441d3ff631d570305 Gerrit-Change-Number: 84109 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84108?usp=email ) Change subject: soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig ...................................................................... soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig CAPID_A, BDSM and BGSM registers may not exist on specific platform, this patch add `HAVE_CAPID_A_REGISTER` and `HAVE_BDSM_BGSM_REGISTER` to select them. Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84108 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h 3 files changed, 19 insertions(+), 0 deletions(-) Approvals: Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 7bb55fe..42d579a 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -43,4 +43,16 @@ help Specify if the SOC has a PAM0 register +config HAVE_CAPID_A_REGISTER + bool + default y + help + Specify if the SOC has the CAPID0_A register that holds DRAM infomations. + +config HAVE_BDSM_BGSM_REGISTER + bool + default y + help + Specify if the SOC has BDSM and BGSM registres. + endif diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 5d9ac15..bca442b 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -78,6 +78,9 @@ if (m == NULL) return; + if (!CONFIG(HAVE_CAPID_A_REGISTER)) + return; + const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A); m->ecc_type = sa_get_ecc_type(capid0_a); @@ -126,7 +129,9 @@ static const struct sa_mem_map_descriptor sa_memory_map[MAX_MAP_ENTRIES] = { { TOUUD, true, "TOUUD" }, { TOLUD, false, "TOLUD" }, +#if CONFIG(HAVE_BDSM_BGSM_REGISTER) { BGSM, false, "BGSM" }, +#endif { TSEG, false, "TSEG" }, }; diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 58d1113..e0f956b 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -58,7 +58,9 @@ enum { SA_TOUUD_REG, SA_TOLUD_REG, +#if CONFIG(HAVE_BDSM_BGSM_REGISTER) SA_BGSM_REG, +#endif SA_TSEG_REG, /* Must be last. */ MAX_MAP_ENTRIES -- To view, visit https://review.coreboot.org/c/coreboot/+/84108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Gerrit-Change-Number: 84108 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: yuchi.chen(a)intel.com. Felix Held has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/84108?usp=email ) Change subject: soc/intel/common/systemagent: select CAPID_A, BDSM and BGSM by Kconfig ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/84108/comment/13398c77_25840e84?us… : PS2, Line 81: if (!CONFIG(HAVE_CAPID_A_REGISTER)) i wonder if this should be moved before the cbmem_find call; not exactly sure how expensive that cbmem_find call is though -- To view, visit https://review.coreboot.org/c/coreboot/+/84108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4d1197b8b1071aefc2ea1ed2f707d769aabab5e4 Gerrit-Change-Number: 84108 Gerrit-PatchSet: 2 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Comment-Date: Mon, 02 Sep 2024 09:06:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_type
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84116?usp=email ) Change subject: soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_type ...................................................................... soc/mediatek: Add EARLY_INIT_PCIE_RESET to early_init_type Add EARLY_INIT_PCIE_RESET for early PERST# de-assertion. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84116 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/early_init.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Jianjun Wang: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/early_init.h b/src/soc/mediatek/common/include/soc/early_init.h index 533dffd..0c4582f 100644 --- a/src/soc/mediatek/common/include/soc/early_init.h +++ b/src/soc/mediatek/common/include/soc/early_init.h @@ -12,6 +12,7 @@ enum early_init_type { EARLY_INIT_PCIE, + EARLY_INIT_PCIE_RESET, EARLY_INIT_MAX, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ab85694e85a4c3f77fefc22efe16734c347a716 Gerrit-Change-Number: 84116 Gerrit-PatchSet: 5 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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