coreboot-gerrit September 2024

coreboot-gerrit@coreboot.org

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3342 discussions

[XS] Change in coreboot[main]: mb/google/ovis/var/deku: Remove DSP setting
by Tony Huang (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Tony Huang has posted comments on this change by Tony Huang. ( https://review.coreboot.org/c/coreboot/+/84139?usp=email ) Change subject: mb/google/ovis/var/deku: Remove DSP setting ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84139/comment/52306fd5_19605594?us… : PS1, Line 14: TEST=emerge-ovis coreboot : check dev beep works > > Drop DSP UPD from ovis baseboard […] I don't have ovis board to confirm. I see ovis has GPP_H19/GPP_H20 calls SOC_I2C_AUD_WFC_SDA/SCL in the schematic, not sure if this change impacts it. Drop DSP UPD and confirm dev beep in deku is fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/84139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia1102dd3dfaa8248b092317edc2a88466adc2bd8 Gerrit-Change-Number: 84139 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Sep 2024 09:34:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84056?usp=email ) Change subject: drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info ...................................................................... drivers/intel/gma: Fix mismatching types for fb_add_framebuffer_info GCC LTO found this. Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84056 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/gma/gma-gfx_init.ads M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb M src/include/framebuffer_info.h M src/lib/edid_fill_fb.c 4 files changed, 15 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/drivers/intel/gma/gma-gfx_init.ads b/src/drivers/intel/gma/gma-gfx_init.ads index 88f64d9..ec1e0ce 100644 --- a/src/drivers/intel/gma/gma-gfx_init.ads +++ b/src/drivers/intel/gma/gma-gfx_init.ads @@ -16,14 +16,14 @@ ---------------------------------------------------------------------------- - function c_fb_add_framebuffer_info + function C_Fb_Add_Framebuffer_Info_Simple (fb_addr: Interfaces.C.size_t; x_resolution : word32; y_resolution : word32; bytes_per_line : word32; bits_per_pixel : word8) - return Interfaces.C.size_t; + return Interfaces.C.int; - pragma import (C, c_fb_add_framebuffer_info, "fb_add_framebuffer_info"); + pragma import (C, C_Fb_Add_Framebuffer_Info_Simple, "fb_add_framebuffer_info_simple"); end GMA.GFX_Init; diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index ae0b0b7..49d0ca4 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -27,6 +27,7 @@ use type word64; use type word32; use type Interfaces.C.size_t; + use type Interfaces.C.int; ports : Port_List; @@ -39,7 +40,7 @@ min_h : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_WIDTH; min_v : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_HEIGHT; - fbinfo : Interfaces.C.size_t; + fbinfo : Interfaces.C.int; begin lightup_ok := 0; @@ -82,7 +83,7 @@ HW.GFX.GMA.Map_Linear_FB (linear_fb_addr, fb); if linear_fb_addr /= 0 then - fbinfo := c_fb_add_framebuffer_info + fbinfo := C_Fb_Add_Framebuffer_Info_Simple (fb_addr => Interfaces.C.size_t (linear_fb_addr), x_resolution => word32 (fb.Width), y_resolution => word32 (fb.Height), diff --git a/src/include/framebuffer_info.h b/src/include/framebuffer_info.h index 83445ec..451d893 100644 --- a/src/include/framebuffer_info.h +++ b/src/include/framebuffer_info.h @@ -14,6 +14,8 @@ struct fb_info *fb_add_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution, uint32_t y_resolution, uint32_t bytes_per_line, uint8_t bits_per_pixel); +int fb_add_framebuffer_info_simple(uintptr_t fb_addr, uint32_t x_res, uint32_t y_res, + uint32_t bytes_per_line, uint8_t bits_per_pixel); void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation); diff --git a/src/lib/edid_fill_fb.c b/src/lib/edid_fill_fb.c index e4fb08c..c72b701 100644 --- a/src/lib/edid_fill_fb.c +++ b/src/lib/edid_fill_fb.c @@ -148,6 +148,13 @@ return info; } +/* Wrapper for Ada to have a simpler function signature */ +int fb_add_framebuffer_info_simple(uintptr_t fb_addr, uint32_t x_res, uint32_t y_res, + uint32_t bytes_per_line, uint8_t bits_per_pixel) +{ + return fb_add_framebuffer_info(fb_addr, x_res, y_res, bytes_per_line, bits_per_pixel) != NULL; +} + void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation) { if (!info) -- To view, visit https://review.coreboot.org/c/coreboot/+/84056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d5a9a86dbb91a5505891a30c6e9072b1b4dfc92 Gerrit-Change-Number: 84056 Gerrit-PatchSet: 17 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[NoOp] Change in blobs[main]: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Tim Van Patten. Hello Karthik Ramasubramanian, Tim Van Patten, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/84180?usp=email to look at the new patch set (#2). Change subject: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries ...................................................................... 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries This PSP verstage is compatible with verified boot. * FW Version: 15826.0.0 * PSP Version: 0.8.C.7B BUG=b:330536985, b:293011193, b:259649666 BRANCH=None TEST=Build Vilboz BIOS image and boot to OS. Ensure that the PSP reports boot mode as in production mode. vilboz-rev3 ~ # cbmem -1 | grep -i psp [INFO ] PSP boot mode: Production Change-Id: Ia0473f0a40d9b10d28c863274f3b25bc968b4c7e Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- D mainboard/google/zork/berknip_psp_verstage.bin.signed A mainboard/google/zork/berknip_psp_verstage.signed.bin D mainboard/google/zork/dalboz_psp_verstage.bin.signed A mainboard/google/zork/dalboz_psp_verstage.signed.bin D mainboard/google/zork/dirinboz_psp_verstage.bin.signed A mainboard/google/zork/dirinboz_psp_verstage.signed.bin D mainboard/google/zork/ezkinil_psp_verstage.bin.signed A mainboard/google/zork/ezkinil_psp_verstage.signed.bin D mainboard/google/zork/gumboz_psp_verstage.bin.signed A mainboard/google/zork/gumboz_psp_verstage.signed.bin D mainboard/google/zork/morphius_psp_verstage.bin.signed A mainboard/google/zork/morphius_psp_verstage.signed.bin D mainboard/google/zork/shuboz_psp_verstage.bin.signed A mainboard/google/zork/shuboz_psp_verstage.signed.bin D mainboard/google/zork/trembyle_psp_verstage.bin.signed A mainboard/google/zork/trembyle_psp_verstage.signed.bin D mainboard/google/zork/vilboz_psp_verstage.bin.signed A mainboard/google/zork/vilboz_psp_verstage.signed.bin D mainboard/google/zork/woomax_psp_verstage.bin.signed A mainboard/google/zork/woomax_psp_verstage.signed.bin 20 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/84180/2 -- To view, visit https://review.coreboot.org/c/blobs/+/84180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ia0473f0a40d9b10d28c863274f3b25bc968b4c7e Gerrit-Change-Number: 84180 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com>

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[NoOp] Change in blobs[main]: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Matt DeVillier, Rob Barnes. Hello Karthik Ramasubramanian, Matt DeVillier, Rob Barnes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/84181?usp=email to look at the new patch set (#2). Change subject: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries ...................................................................... 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries This PSP verstage is compatible with verified boot. * FW Version: 15874.0.0 * PSP Version: 0.11.11.75 BUG=b:338615043 BRANCH=None TEST=Build Dewatt BIOS image and boot to OS. Ensure that the PSP boots in production mode. Change-Id: Ida220410a4b896b746dda74258fa45a51524dbc2 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M mainboard/google/guybrush/dewatt_psp_verstage.signed.bin M mainboard/google/guybrush/guybrush_psp_verstage.signed.bin M mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin 3 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/81/84181/2 -- To view, visit https://review.coreboot.org/c/blobs/+/84181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ida220410a4b896b746dda74258fa45a51524dbc2 Gerrit-Change-Number: 84181 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com>

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[NoOp] Change in blobs[main]: 3rdparty/blobs/mb/google/zork: Update PSP signing token
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

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[NoOp] Change in blobs[main]: CHROMIUM: 3rdparty/blobs/mb/google/guybrush: Update signed PSP versta...
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Matt DeVillier, Rob Barnes. Hello Matt DeVillier, Rob Barnes, Karthik Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/blobs/+/84181?usp=email to review the following change. Change subject: CHROMIUM: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries ...................................................................... CHROMIUM: 3rdparty/blobs/mb/google/guybrush: Update signed PSP verstage binaries This PSP verstage is compatible with verified boot. * FW Version: 15874.0.0 * PSP Version: 0.11.11.75 BUG=b:338615043 BRANCH=None TEST=Build Dewatt BIOS image and boot to OS. Ensure that the PSP boots in production mode. Change-Id: Ida220410a4b896b746dda74258fa45a51524dbc2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Commit-Queue: Rob Barnes <robbarnes(a)google.com> Tested-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> --- M mainboard/google/guybrush/dewatt_psp_verstage.signed.bin M mainboard/google/guybrush/guybrush_psp_verstage.signed.bin M mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin 3 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/81/84181/1 diff --git a/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin b/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin index a2b5bc0..ef2be8f 100644 --- a/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin +++ b/mainboard/google/guybrush/dewatt_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin b/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin index ccdf85a..8653223 100644 --- a/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin +++ b/mainboard/google/guybrush/guybrush_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin b/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin index 28468f7..784ed67 100644 --- a/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin +++ b/mainboard/google/guybrush/nipperkin_psp_verstage.signed.bin Binary files differ -- To view, visit https://review.coreboot.org/c/blobs/+/84181?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ida220410a4b896b746dda74258fa45a51524dbc2 Gerrit-Change-Number: 84181 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[NoOp] Change in blobs[main]: CHROMIUM: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage b...
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

Attention is currently required from: Karthik Ramasubramanian, Tim Van Patten. Hello Tim Van Patten, Karthik Ramasubramanian, I'd like you to do a code review. Please visit https://review.coreboot.org/c/blobs/+/84180?usp=email to review the following change. Change subject: CHROMIUM: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries ...................................................................... CHROMIUM: 3rdparty/blobs/mb/google/zork: Update signed PSP verstage binaries This PSP verstage is compatible with verified boot. * FW Version: 15826.0.0 * PSP Version: 0.8.C.7B BUG=b:330536985, b:293011193, b:259649666 BRANCH=None TEST=Build Vilboz BIOS image and boot to OS. Ensure that the PSP reports boot mode as in production mode. vilboz-rev3 ~ # cbmem -1 | grep -i psp [INFO ] PSP boot mode: Production Change-Id: Ia0473f0a40d9b10d28c863274f3b25bc968b4c7e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Reviewed-by: Tim Van Patten <timvp(a)google.com> --- D mainboard/google/zork/berknip_psp_verstage.bin.signed A mainboard/google/zork/berknip_psp_verstage.signed.bin D mainboard/google/zork/dalboz_psp_verstage.bin.signed A mainboard/google/zork/dalboz_psp_verstage.signed.bin D mainboard/google/zork/dirinboz_psp_verstage.bin.signed A mainboard/google/zork/dirinboz_psp_verstage.signed.bin D mainboard/google/zork/ezkinil_psp_verstage.bin.signed A mainboard/google/zork/ezkinil_psp_verstage.signed.bin D mainboard/google/zork/gumboz_psp_verstage.bin.signed A mainboard/google/zork/gumboz_psp_verstage.signed.bin D mainboard/google/zork/morphius_psp_verstage.bin.signed A mainboard/google/zork/morphius_psp_verstage.signed.bin D mainboard/google/zork/shuboz_psp_verstage.bin.signed A mainboard/google/zork/shuboz_psp_verstage.signed.bin D mainboard/google/zork/trembyle_psp_verstage.bin.signed A mainboard/google/zork/trembyle_psp_verstage.signed.bin D mainboard/google/zork/vilboz_psp_verstage.bin.signed A mainboard/google/zork/vilboz_psp_verstage.signed.bin D mainboard/google/zork/woomax_psp_verstage.bin.signed A mainboard/google/zork/woomax_psp_verstage.signed.bin 20 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/80/84180/1 diff --git a/mainboard/google/zork/berknip_psp_verstage.bin.signed b/mainboard/google/zork/berknip_psp_verstage.bin.signed deleted file mode 100644 index ffe9816..0000000 --- a/mainboard/google/zork/berknip_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/berknip_psp_verstage.signed.bin b/mainboard/google/zork/berknip_psp_verstage.signed.bin new file mode 100644 index 0000000..9967182 --- /dev/null +++ b/mainboard/google/zork/berknip_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/dalboz_psp_verstage.bin.signed b/mainboard/google/zork/dalboz_psp_verstage.bin.signed deleted file mode 100644 index 45a7364..0000000 --- a/mainboard/google/zork/dalboz_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/dalboz_psp_verstage.signed.bin b/mainboard/google/zork/dalboz_psp_verstage.signed.bin new file mode 100644 index 0000000..3966342 --- /dev/null +++ b/mainboard/google/zork/dalboz_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/dirinboz_psp_verstage.bin.signed b/mainboard/google/zork/dirinboz_psp_verstage.bin.signed deleted file mode 100644 index 20f7846..0000000 --- a/mainboard/google/zork/dirinboz_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/dirinboz_psp_verstage.signed.bin b/mainboard/google/zork/dirinboz_psp_verstage.signed.bin new file mode 100644 index 0000000..26372a8 --- /dev/null +++ b/mainboard/google/zork/dirinboz_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/ezkinil_psp_verstage.bin.signed b/mainboard/google/zork/ezkinil_psp_verstage.bin.signed deleted file mode 100644 index f6bcb60..0000000 --- a/mainboard/google/zork/ezkinil_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/ezkinil_psp_verstage.signed.bin b/mainboard/google/zork/ezkinil_psp_verstage.signed.bin new file mode 100644 index 0000000..53d28fd --- /dev/null +++ b/mainboard/google/zork/ezkinil_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/gumboz_psp_verstage.bin.signed b/mainboard/google/zork/gumboz_psp_verstage.bin.signed deleted file mode 100644 index 2e67e2a..0000000 --- a/mainboard/google/zork/gumboz_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/gumboz_psp_verstage.signed.bin b/mainboard/google/zork/gumboz_psp_verstage.signed.bin new file mode 100644 index 0000000..1f5565b --- /dev/null +++ b/mainboard/google/zork/gumboz_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/morphius_psp_verstage.bin.signed b/mainboard/google/zork/morphius_psp_verstage.bin.signed deleted file mode 100644 index 9c349d4..0000000 --- a/mainboard/google/zork/morphius_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/morphius_psp_verstage.signed.bin b/mainboard/google/zork/morphius_psp_verstage.signed.bin new file mode 100644 index 0000000..6f3867e --- /dev/null +++ b/mainboard/google/zork/morphius_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/shuboz_psp_verstage.bin.signed b/mainboard/google/zork/shuboz_psp_verstage.bin.signed deleted file mode 100644 index 49559c5..0000000 --- a/mainboard/google/zork/shuboz_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/shuboz_psp_verstage.signed.bin b/mainboard/google/zork/shuboz_psp_verstage.signed.bin new file mode 100644 index 0000000..991f867 --- /dev/null +++ b/mainboard/google/zork/shuboz_psp_verstage.signed.bin Binary files differ diff --git a/mainboard/google/zork/trembyle_psp_verstage.bin.signed b/mainboard/google/zork/trembyle_psp_verstage.bin.signed deleted file mode 100644 index 95644f1..0000000 --- a/mainboard/google/zork/trembyle_psp_verstage.bin.signed +++ /dev/null Binary files differ diff --git a/mainboard/google/zork/trembyle_psp_verstage.signed.bin b/mainboard/google/zork/trembyle_psp_verstage.signed.bin new file mode 100644 index 0000000..4189a06 --- /dev/null +++ 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index 0000000..f966d56 --- /dev/null +++ b/mainboard/google/zork/woomax_psp_verstage.signed.bin Binary files differ -- To view, visit https://review.coreboot.org/c/blobs/+/84180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: Ia0473f0a40d9b10d28c863274f3b25bc968b4c7e Gerrit-Change-Number: 84180 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[NoOp] Change in blobs[main]: CHROMIUM: 3rdparty/blobs/mb/google/zork: Update PSP signing token
by Jon Murphy (Code Review) 02 Sep '24

02 Sep '24

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[XS] Change in coreboot[main]: mb/google/cherry: Complete PCIe reset in romstage
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84118?usp=email ) Change subject: mb/google/cherry: Complete PCIe reset in romstage ...................................................................... mb/google/cherry: Complete PCIe reset in romstage De-assert PERST# at romstage to reduce the waiting time in ramstage. Before ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` After ``` [INFO ] wait_perst_done: PCIe early PERST# de-assertion is not done, de-assert PERST# now [DEBUG] wait_perst_asserted: 457568 us elapsed since assert PERST# [DEBUG] wait_perst_done: 163413 us elapsed since de-assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (1 tries) ``` BUG=none TEST=boot from NVMe Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84118 Reviewed-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/romstage.c M src/soc/mediatek/mt8195/Makefile.mk 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: Jianjun Wang: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c index f375867..ab05220 100644 --- a/src/mainboard/google/cherry/romstage.c +++ b/src/mainboard/google/cherry/romstage.c @@ -8,6 +8,7 @@ #include <soc/mt6315.h> #include <soc/mt6359p.h> #include <soc/mt6360.h> +#include <soc/pcie.h> #include <soc/pll_common.h> #include <soc/pmif.h> #include <soc/rtc.h> @@ -33,6 +34,8 @@ mt6360_init(I2C7); clk_buf_init(); rtc_boot(); + if (CONFIG(PCI)) + mtk_pcie_deassert_perst(); mtk_dram_init(); scp_rsi_enable(); } diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index a37f715..a3b002e 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -36,6 +36,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c romstage-y += mt6360.c romstage-y += mt6691.c +romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += apusys.c -- To view, visit https://review.coreboot.org/c/coreboot/+/84118?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a73bd574ae8f9f4e624846ce8b901a7d2209e78 Gerrit-Change-Number: 84118 Gerrit-PatchSet: 8 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset
by Felix Held (Code Review) 02 Sep '24

02 Sep '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84117?usp=email ) Change subject: soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset ...................................................................... soc/mediatek: Add mtk_pcie_deassert_perst for early PCIe reset Even we assert PRSET# early to save the delay between PERST# assertion and de-assertion. MediaTek PCIe driver still takes 47ms waiting for PCIe link up. (1ms delay for each try) ``` [INFO ] mtk_pcie_domain_enable: PCIe link up success (47 tries) ``` Refactor common/pcie.c and add mtk_pcie_deassert_perst for early PCIe reset. So we can de-assert PERST# at early stage to improve the boot time. BUG=b:361728592 TEST=emerge-cherry coreboot Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84117 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jianjun Wang <jianjun.wang(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/pcie_common.h M src/soc/mediatek/common/pcie.c 2 files changed, 54 insertions(+), 18 deletions(-) Approvals: Jianjun Wang: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/pcie_common.h b/src/soc/mediatek/common/include/soc/pcie_common.h index c34bc4e..cfefae2 100644 --- a/src/soc/mediatek/common/include/soc/pcie_common.h +++ b/src/soc/mediatek/common/include/soc/pcie_common.h @@ -23,5 +23,6 @@ void mtk_pcie_domain_set_resources(struct device *dev); void mtk_pcie_domain_enable(struct device *dev); void mtk_pcie_reset(uintptr_t base_reg, bool enable); +void mtk_pcie_deassert_perst(void); #endif diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index e796dc1..9269fbd 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -266,24 +266,9 @@ return CB_SUCCESS; } -void mtk_pcie_domain_enable(struct device *dev) +static void wait_perst_asserted(uintptr_t base) { - const mtk_soc_config_t *config = config_of(dev); - const struct mtk_pcie_config *conf = &config->pcie_config; - const char *ltssm_state; long perst_time_us; - size_t tries = 0; - uint32_t val; - - /* Set as RC mode */ - setbits32p(conf->base + PCIE_SETTING_REG, PCIE_RC_MODE); - - /* Set class code */ - clrsetbits32p(conf->base + PCIE_PCI_IDS_1, GENMASK(31, 8), - PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); - - /* Mask all INTx interrupts */ - clrbits32p(conf->base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n", @@ -301,7 +286,7 @@ printk(BIOS_WARNING, "%s: PCIe early init data not found, sleeping 100ms\n", __func__); - mtk_pcie_reset(conf->base, true); + mtk_pcie_reset(base, true); } else { printk(BIOS_WARNING, "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", @@ -310,9 +295,59 @@ udelay(min_perst_time_us - perst_time_us); } +} +static void deassert_perst(uintptr_t base) +{ + /* Set as RC mode */ + setbits32p(base + PCIE_SETTING_REG, PCIE_RC_MODE); + + /* Set class code */ + clrsetbits32p(base + PCIE_PCI_IDS_1, GENMASK(31, 8), + PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8)); + + /* Mask all INTx interrupts */ + clrbits32p(base + PCIE_INT_ENABLE_REG, PCIE_INTX_ENABLE); + + /* Above registers must be set before de-asserting PERST# */ /* De-assert reset signals */ - mtk_pcie_reset(conf->base, false); + mtk_pcie_reset(base, false); +} + +static void wait_perst_done(uintptr_t base) +{ + long perst_time_us; + + wait_perst_asserted(base); + + perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE_RESET); + printk(BIOS_DEBUG, "%s: %ld us elapsed since de-assert PERST#\n", + __func__, perst_time_us); + + if (!perst_time_us) { + printk(BIOS_INFO, "%s: PCIe early PERST# de-assertion is not done, " + "de-assert PERST# now\n", __func__); + deassert_perst(base); + } +} + +void mtk_pcie_deassert_perst(void) +{ + uintptr_t base = mtk_pcie_get_controller_base(0); + + wait_perst_done(base); + early_init_save_time(EARLY_INIT_PCIE_RESET); +} + +void mtk_pcie_domain_enable(struct device *dev) +{ + const mtk_soc_config_t *config = config_of(dev); + const struct mtk_pcie_config *conf = &config->pcie_config; + const char *ltssm_state; + size_t tries = 0; + uint32_t val; + + wait_perst_done(conf->base); if (!retry(100, (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & -- To view, visit https://review.coreboot.org/c/coreboot/+/84117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I008e95263bfaf0119353382c2d2ce5ce29c6a382 Gerrit-Change-Number: 84117 Gerrit-PatchSet: 7 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2024