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Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/84236/comment/efc32214_a14b8369?us… :
PS1, Line 519: add %edx, %eax
> Seems better, did you run a debugger to verify that the registers through this logic ?
I don't have HW debugger to run it. But used software analyzer to ensure the register values are correct.
> Now we 3 instructions instead of 3 with an extra label. I had a version like this originally that I discarded as I preferred to not introduce a new label.
> I let you decide if you want to proceed with this. I don't see any sinificant improvement with this new version but I am not opposed to it.
Snippet 1
```
movl $0x01, %ecx ; Move the value 1 into the ECX register
cmp $0x00, %edx ; Compare the value in the EDX register with 0
cmovne %ecx, %edx ; If EDX is not equal to 0, move the value in ECX (which is 1) into EDX
add %edx, %eax ; Add the value in EDX to the value in EAX
```
Snippet 2
```
testl %edx, %edx ; Perform a bitwise AND on EDX with itself, setting flags based on the result
jz skip_increment ; If the zero flag is set (meaning EDX was 0), jump to the skip_increment label
incl %eax ; Increment the value in EAX by 1
skip_increment: ; Label to jump to if EDX was 0
```
Both snippets essentially achieve the same goal:
- If the value in %edx is zero, don't modify %eax.
- If the value in %edx is non-zero, increment %eax by 1.
However, the second snippet (testl/jz/incl) is generally considered to be better optimized for a few reasons:
Fewer Instructions: It uses three instructions compared to the four in the first snippet. Fewer instructions generally lead to faster execution.
No Data Movement: The second snippet doesn't need to move any immediate values (like the 0x01) into registers, which can save some execution time.
Leverages Flags: The testl instruction efficiently sets flags based on the value in %edx, and the jz instruction directly uses those flags for conditional branching. This can be more streamlined than the cmp/cmovne approach. Additionally, cmovne is complex instruction which have potential for pipeline stalls.
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Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84236/comment/b7363a5e_5bb60239?us… :
PS3, Line 14: lesser
less?
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Change subject: src/device: Add more condition to check valid PCI device id
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84228/comment/da011762_5635bcb6?us… :
PS2, Line 12: Below are invalid PCI device id cases
: VID: 0x0 or 0xffff
: DID: 0x0 or 0xffff
> Yes, there is issue in valid VID with 0x0 DID in PSS environment. UEFI bootloader ignores the device by checking the case but coreboot did not.
Please don't bring the changes to support simics. This can be fixed by simics team by adding valid VID and DID. we don't need to add such configuration in coreboot.
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Change subject: src/device: Add more condition to check valid PCI device id
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84228/comment/1c32fde5_d2fac621?us… :
PS2, Line 12: Below are invalid PCI device id cases
: VID: 0x0 or 0xffff
: DID: 0x0 or 0xffff
> can you please highlight why some device missed to update VID/DID. […]
Yes, there is issue in valid VID with 0x0 DID in PSS environment. UEFI bootloader ignores the device by checking the case but coreboot did not.
File src/device/pci_device.c:
https://review.coreboot.org/c/coreboot/+/84228/comment/12afeb27_20548601?us… :
PS2, Line 1225: dummy.vendor = id & 0xffff;
: dummy.device = (id >> 16) & 0xffff;
: if ((dummy.vendor == 0x0000) || (dummy.vendor == 0xffff) ||
: (dummy.device == 0x0000) || (dummy.device == 0xffff)) {
: printk(BIOS_SPEW, "device %s [0x%04x/0x%04x] is not found.\n",
: dev_path(&dummy), dummy.vendor, dummy.device);
:
> why don't u make an inline function, as this test is used at multiple places?
Acknowledged
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Change subject: soc/intel/common/block/pmc: Add GPE1 functions
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84104/comment/44595745_8352f21b?us… :
PS11, Line 15: and check if GPE1 sts bits have been printed during boot.
Paste the new debug messages?
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Change subject: mb/google/hatch: Add FP enable for Dratini
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83745/comment/e4cf00a2_ed6b5e67?us… :
PS7, Line 7: mb/google/hatch: Add FP enable for Dratini
Use `mb/google/hatch/var/dratini:`?
https://review.coreboot.org/c/coreboot/+/83745/comment/ac49013f_cdaec6fd?us… :
PS7, Line 18: Disable test SKU, flash on Dratini, test FP.
Any log messages?
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Change subject: make same cpu pyhsical address
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84230/comment/296f6b7f_f3557c68?us… :
PS2, Line 7: make same cpu pyhsical address
:
: 2 funtions are used to get cpu physical address like below.
: cpu_phys_address_size
: soc_phys_address_size
: And If CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH is defined,
: it can return different address size like below
: example)
: coreboot log: CPU physical address size: 46 bits
: OS log : DMAR: Host address width 42
: So, need to make one API to use same physical address.
:
> Yes, the return value is overrided by CONFIG_SOC_PHYSICAL_ADDRESS_WIDT only in soc_phys_address_size […]
This change still supports overriding address width like current implementation.
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Change subject: tree: Use boolean for lpss_s0ix_enable
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/google/brox/variants/brox:remove PL4 value modification
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83662/comment/8208f60c_8882bee1?us… :
PS3, Line 7: mb/google/brox/variants/brox:remove PL4 value modification
Please add a space after the colon (:).
https://review.coreboot.org/c/coreboot/+/83662/comment/9e0a11d2_8f87c169?us… :
PS3, Line 9: Remove PL4 value modification based on PsysPL3 value.
Why?
https://review.coreboot.org/c/coreboot/+/83662/comment/d25dafd6_d36f10df?us… :
PS3, Line 13: TEST=Built and boot on brox system
What difference can be seen?
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