coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: lib/string: Add strncat() and strcat() functions
by Yu-Ping Wu (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Jakub Czapiga, Yu-Ping Wu. Hello Jakub Czapiga, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83765?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Jakub Czapiga, Verified+1 by build bot (Jenkins) Change subject: lib/string: Add strncat() and strcat() functions ...................................................................... lib/string: Add strncat() and strcat() functions An upcoming vboot feature [1] will need strcat() to be defined in string.h. Therefore, implement strncat() and strcat() in coreboot. Note that these two functions already exist in libpayload. [1] https://chromium-review.googlesource.com/c/chromiumos/platform/vboot_refere… Change-Id: If02fce0eafb4f6fa01d8bab17d87a32360f4ac83 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> --- M src/include/string.h M src/lib/string.c M tests/lib/string-test.c 3 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/83765/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If02fce0eafb4f6fa01d8bab17d87a32360f4ac83 Gerrit-Change-Number: 83765 Gerrit-PatchSet: 4 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: mb/google/brya/var/trulo: Update ISH GPIO's configuration
by Eric Lai (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Rishika Raj, Varun Upadhyay. Eric Lai has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83781?usp=email ) Change subject: mb/google/brya/var/trulo: Update ISH GPIO's configuration ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Gerrit-Change-Number: 83781 Gerrit-PatchSet: 3 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 07 Aug 2024 02:22:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/trulo/var/orisa: Update ISH GPIO's configuration
by Eric Lai (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Deepti Deshatty, Dinesh Gehlot, Kapil Porwal, Li Feng, Li1 Feng, Nick Vaccaro, Rishika Raj, Varun Upadhyay. Eric Lai has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83656?usp=email ) Change subject: mb/google/trulo/var/orisa: Update ISH GPIO's configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Gerrit-Change-Number: 83656 Gerrit-PatchSet: 5 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li Feng <li1.feng(a)intel.corp-partner.google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Li Feng <li1.feng(a)intel.corp-partner.google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Wed, 07 Aug 2024 02:22:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence
by Roger Wang (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83792?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence ...................................................................... mb/google/nissa/var/sundance: Adjust WWAN GPIO sequence Remove the WWAN_RST_L (GPP_F12) in bootblock phase BUG=b:357764679 TEST=Build and verified test result by EE team Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/sundance/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83792/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Gerrit-Change-Number: 83792 Gerrit-PatchSet: 2 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Adjust WWAN GPIO enable sequence for DV...
by Roger Wang (Code Review) 07 Aug '24

07 Aug '24

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83792?usp=email ) Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO enable sequence for DVT build ...................................................................... mb/google/nissa/var/sundance: Adjust WWAN GPIO enable sequence for DVT build Remove the WWAN_RST_L (GPP_F12) in bootblock phase BUG=b:357764679 TEST=Build and verified test result by EE team Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/sundance/gpio.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83792/1 diff --git a/src/mainboard/google/brya/variants/sundance/gpio.c b/src/mainboard/google/brya/variants/sundance/gpio.c index bd36f05..107fa77 100644 --- a/src/mainboard/google/brya/variants/sundance/gpio.c +++ b/src/mainboard/google/brya/variants/sundance/gpio.c @@ -66,8 +66,6 @@ PAD_CFG_GPO(GPP_D6, 0, DEEP), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), - /* F12 : WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83792?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551 Gerrit-Change-Number: 83792 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC722 codec
by Anil Kumar K (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Naveen M, Paul Menzel, Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81920?usp=email to look at the new patch set (#7). Change subject: drivers/soundwire: Support Realtek ALC722 codec ...................................................................... drivers/soundwire: Support Realtek ALC722 codec This patch adds SoundWire driver to support ALC722 audio codec. The existing ALC711 codec driver is refactored to include support for ALC722 device based on config flag. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc711 register "desc" = ""Headset Codec"" device generic 0.1 on end end TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback using speaker output. reference datasheet : Realtek ALC722-CG ver. 0.56 Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 --- M src/drivers/soundwire/alc711/Kconfig M src/drivers/soundwire/alc711/Makefile.mk M src/drivers/soundwire/alc711/alc711.c M src/include/mipi/ids.h 4 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81920/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Gerrit-Change-Number: 81920 Gerrit-PatchSet: 7 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-CC: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: [Test Only] mb/google/rex/karis: Set PCIE WLAN bluetooth companion de...
by Tyler Wang (Code Review) 07 Aug '24

07 Aug '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83791?usp=email ) Change subject: [Test Only] mb/google/rex/karis: Set PCIE WLAN bluetooth companion device ...................................................................... [Test Only] mb/google/rex/karis: Set PCIE WLAN bluetooth companion device To publish the Bluetooth Regulator Domain Settings under the right ACPI device scope, the wifi generic driver requires the bluetooth companion to be set accordingly. BUG=b:345373187 TEST=none Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/83791/1 diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index 57c7c73..99183d9 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -528,6 +528,7 @@ chip drivers/wifi/generic register "wake" = "GPE0_DW2_09" register "add_acpi_dma_property" = "true" + use usb2_port10 as bluetooth_companion device pci 00.0 on probe WIFI_TYPE WIFI_PCIE end -- To view, visit https://review.coreboot.org/c/coreboot/+/83791?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28541e7a23dd486d3e0ec38ee89e1ab13595fc72 Gerrit-Change-Number: 83791 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/dedede:Add fw_config control to wifi driver BUG=b:351968527
by Tongtong Pan (Code Review) 07 Aug '24

07 Aug '24

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83790?usp=email ) Change subject: mb/google/dedede:Add fw_config control to wifi driver BUG=b:351968527 ...................................................................... mb/google/dedede:Add fw_config control to wifi driver BUG=b:351968527 Change-Id: I4c7e2fb6fe38c048f29cb8255c4b125ea284de5b Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/awasuki/overridetree.cb M src/mainboard/google/dedede/variants/awasuki/ramstage.c M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h M src/soc/intel/jasperlake/chip.h 5 files changed, 62 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/83790/1 diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index 148840f..9fca591 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -1,3 +1,11 @@ +fw_config + field WIFI 8 9 + option UNKNOWN 0 + option WIFI_6 1 + option WIFI_6E 2 + end +end + chip soc/intel/jasperlake # USB Port Configuration register "usb2_ports[1]" = "USB2_PORT_EMPTY" @@ -71,10 +79,6 @@ # Set xHCI LFPS period sampling off time register "xhci_lfps_sampling_offtime_ms" = "0" - # Disable SD card - register "sdcard_cd_gpio" = "0" - register "SdCardPowerEnableActiveHigh" = "0" - device domain 0 on device pci 04.0 on chip drivers/intel/dptf @@ -161,6 +165,7 @@ end end # USB xHCI device pci 14.3 on + probe WIFI WIFI_6E chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" register "enable_cnvi_ddr_rfim" = "true" @@ -181,24 +186,18 @@ end # I2C 0 device pci 15.1 off end # I2C 1 device pci 15.2 on - probe TOUCHSCREEN TOUCHSCREEN_PRESENT - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" - register "detect" = "1" - register "reset_gpio" = + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)" - register "reset_delay_ms" = "25" - register "reset_off_delay_ms" = "8" - register "stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" - register "stop_delay_ms" = "280" - register "stop_off_delay_ms" = "2" - register "enable_gpio" = + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" - register "enable_delay_ms" = "7" - register "has_power_resource" = "1" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" device i2c 10 on end end end # I2C 2 @@ -216,6 +215,7 @@ end end # I2C 4 device pci 1c.7 on + probe WIFI WIFI_6 chip drivers/wifi/generic register "wake" = "GPE0_DW2_03" device pci 00.0 on end diff --git a/src/mainboard/google/dedede/variants/awasuki/ramstage.c b/src/mainboard/google/dedede/variants/awasuki/ramstage.c index 418826c..1591ebb 100644 --- a/src/mainboard/google/dedede/variants/awasuki/ramstage.c +++ b/src/mainboard/google/dedede/variants/awasuki/ramstage.c @@ -4,6 +4,8 @@ #include <fw_config.h> #include <soc/soc_chip.h> #include <soc/gpio.h> +#include <console/console.h> +#include <chip.h> static const struct pad_config ts_disable_pad[] = { /* A11 : TOUCH_RPT_EN */ @@ -22,16 +24,40 @@ PAD_NC(GPP_H5, NONE), }; +static const struct pad_config wifi_pcie_enable_pad[] = { + /* B8 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* D3 : WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_D3, NONE, DEEP, EDGE_SINGLE), +}; + void variant_devtree_update(void) { struct soc_intel_jasperlake_config *cfg = config_of_soc(); if (fw_config_probe(FW_CONFIG(EXT_VR, EXT_VR_ABSENT))) { + printk(BIOS_INFO, "EXT_VR_ABSENT.\n"); cfg->disable_external_bypass_vr = 1; } if (!fw_config_probe(FW_CONFIG(TOUCHSCREEN, TOUCHSCREEN_PRESENT))) { + printk(BIOS_INFO, "TOUCHSCREEN_ABSENT.\n"); cfg->SerialIoI2cMode[PchSerialIoIndexI2C2] = PchSerialIoDisabled; gpio_configure_pads(ts_disable_pad, ARRAY_SIZE(ts_disable_pad)); } + + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6))) { + printk(BIOS_INFO, "Enable PCie based Wifi GPIO pins.\n"); + gpio_configure_pads(wifi_pcie_enable_pad,ARRAY_SIZE(wifi_pcie_enable_pad)); + } +} + +void variant_update_soc_chip_config(struct soc_intel_jasperlake_config *config) +{ + if (!fw_config_probe(FW_CONFIG(WIFI, WIFI_6E))) { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + printk(BIOS_INFO, "CNVi bluetooth audio offload disabled by fw_config\n"); + config->cnvi_bt_audio_offload = false; + } } diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 4a234a8..9185d33 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,13 +19,9 @@ option TOUCHSCREEN_ABSENT 0 option TOUCHSCREEN_PRESENT 1 end - field TABLETMODE 10 - option TABLETMODE_DISABLED 0 - option TABLETMODE_ENABLED 1 - end - field LTE 11 - option LTE_ABSENT 0 - option LTE_PRESENT 1 + field TABLETMODE 10 + option TABLETMODE_DISABLED 0 + option TABLETMODE_ENABLED 1 end field AUDIO_AMP 14 16 option UNPROVISIONED 0 @@ -34,6 +30,10 @@ option RT1015P_AUTO 3 option ALC5650 4 end + field LTE 11 + option LTE_ABSENT 0 + option LTE_PRESENT 1 + end field EXT_VR 18 option EXT_VR_PRESENT 0 option EXT_VR_ABSENT 1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bb9fd5d..47b331c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -6,6 +6,7 @@ #include <soc/gpio.h> #include <stdint.h> #include <acpi/acpi_device.h> +#include <chip.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ @@ -48,6 +49,7 @@ /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +void variant_update_soc_chip_config(struct soc_intel_jasperlake_config *config); struct psys_config { /* diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index f8d069e..3daa542 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -453,6 +453,13 @@ */ bool disable_external_bypass_vr; + /* CNVi BT Core Enable/Disable */ + bool cnvi_bt_core; + + /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ + bool cnvi_bt_audio_offload; + + /* * Core Display Clock Frequency selection, FSP UPD CdClock values + 1 * -- To view, visit https://review.coreboot.org/c/coreboot/+/83790?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c7e2fb6fe38c048f29cb8255c4b125ea284de5b Gerrit-Change-Number: 83790 Gerrit-PatchSet: 1 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/common: Add SoC QDF read function
by Jamie Ryu (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Hannah Williams. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83785?usp=email to look at the new patch set (#4). Change subject: soc/intel/common: Add SoC QDF read function ...................................................................... soc/intel/common: Add SoC QDF read function This adds pmc_read_qdf to read and print Intel SoC QDF information. This is supported from Intel Panther Lake SoC. Change-Id: Icad129e8889bac6bb96fb99dde089bcc4426d274 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/83785/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icad129e8889bac6bb96fb99dde089bcc4426d274 Gerrit-Change-Number: 83785 Gerrit-PatchSet: 4 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/common: Add PMC command to access SoC registers
by Bora Guvendik (Code Review) 07 Aug '24

07 Aug '24

Attention is currently required from: Jamie Ryu. Bora Guvendik has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/83784?usp=email ) Change subject: soc/intel/common: Add PMC command to access SoC registers ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I927da1a97e6dad4ee54c4d2256fea5813a0ce43d Gerrit-Change-Number: 83784 Gerrit-PatchSet: 3 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Comment-Date: Wed, 07 Aug 2024 00:39:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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