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Change subject: soc/intel/xeon_sp: Reserve MMIO high range
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83538/comment/26a0fd93_abd4ff11?us… :
PS4, Line 13: belonged
> belong*ing*?
Done
https://review.coreboot.org/c/coreboot/+/83538/comment/bbb816ea_9b947c88?us… :
PS4, Line 16:
> Paste an example of cluttered coverage?
Done
https://review.coreboot.org/c/coreboot/+/83538/comment/5231102d_d7e80f3a?us… :
PS4, Line 31: tsc: Detected 2000.000 MHz processor
: last_pfn = 0x2080000 max_arch_pfn = 0x10000000000
: x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT
: WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM.
: ------------[ cut here ]------------
: WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9
: ...
: Call Trace:
: ? 0xffffffff8f600000
: ? setup_arch+0x4bb/0xaed
: ? printk+0x53/0x6a
: ? start_kernel+0x55/0x507
: ? load_ucode_intel_bsp+0x1c/0x4d
: ? secondary_startup_64_no_verify+0xc2/0xcb
: random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0
: ---[ end trace 0e56686fd458f0c5 ]---
: update e820 for mtrr
: modified physical RAM map:
: modified: [mem 0x0000000000000000-0x0000000000000fff] reserved
: ...
: modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved
: last_pfn = 0x6354e max_arch_pfn = 0x10000000000
: Memory KASLR using RDRAND RDTSC...
: x2apic: enabled by BIOS, switching to x2apic ops
: Using GB pages for direct mapping
: ...
: Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff]
: DMA zone: 28769 pages in unavailable ranges
: DMA32 zone: 19122 pages in unavailable ranges
: BUG: unable to handle page fault for address: ff24b56eba60cff8
: BAD
: Oops: 0000 [#1] SMP NOPTI
: CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2
: ...
: Call Trace:
: ? set_pte_vaddr_p4d+0x24/0x35
: ? __native_set_fixmap+0x21/0x28
: ? map_vsyscall+0x35/0x56
: ? setup_arch+0xa00/0xaed
: ? printk+0x53/0x6a
: ? start_kernel+0x55/0x507
: ? load_ucode_intel_bsp+0x1c/0x4d
: ? secondary_startup_64_no_verify+0xc2/0xcb
: CR2: ff24b56eba60cff8
: ---[ end trace 0e56686fd458f0c6 ]---
: RIP: 0010:fill_pud+0xa/0x62
: ...
: Kernel panic - not syncing: Attempted to kill the idle task!
: ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
> Linux 5.10.50 seems pretty old. Does it happen with current Linux 6. […]
Yes, in 6.10.0, hangs at below sites without further logs.
... version: 5
... bit width: 48
... generic registers: 8
... value mask: 0000ffffffffffff
... max period: 00007fffffffffff
... fixed-purpose events: 3
... event mask: 00000007000000ff
signal: max sigframe size: 1360
Estimated ratio of average max frequency by base frequency (times 1024): 1455
rcu: Hierarchical SRCU implementation.
rcu: Max phase no-delay instances is 1000.
smp: Bringing up secondary CPUs ...
smpboot: x86: Booting SMP configuration:
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Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.
Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83538?usp=email
to look at the new patch set (#5).
Change subject: soc/intel/xeon_sp: Reserve MMIO high range
......................................................................
soc/intel/xeon_sp: Reserve MMIO high range
Xeon-SP supports MMIO high range, a.k.a. MMIO range above 4G. FSP will
assign domain MMIO high windows from this range.
However, there will be unassigned parts among these high windows for
non-domain device usage (e.g. misc devices belonging to an IIO stack
but not belonged to any PCIe domains under that stack). This will cause
segmentation in MTRR UC coverage.
For example, in SPR-XCC where only CPM0/HQM0 are supported and
instantiated to PCIe domains, MMIO ranges are still reserved for
CPM1/HQM1. See more at src/soc/intel/xeon_sp/spr/ioat.c.
Reserve MMIO high range as a whole under domain0/00:0.0. During MTRR
calculation, this reservation will connect the discontinued domain MMIO
high windows together to form one continuous range, and save MTRR
register usage from inadequacy.
This change is initially raised for SPR but could be effective for GNR
as well.
TESTED = Build and boot in intel/archercity CRB, MTRR register usage
decreases from 7 to 3 in 2S system.
TESTED = Only setting MTRR for below 4GB ranges test fails with
LinuxBoot on SPR (through x86_setup_mtrrs_with_detect_no_above_4gb)
tsc: Detected 2000.000 MHz processor
last_pfn = 0x2080000 max_arch_pfn = 0x10000000000
x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT
WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing 129024MB of RAM.
------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at arch/x86/kernel/cpu/mtrr/cleanup.c:978 mtrr_trim_uncached_memory+0x2b9/0x2f9
...
Call Trace:
? 0xffffffff8f600000
? setup_arch+0x4bb/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
random: get_random_bytes called from init_oops_id+0x1d/0x2c with crng_init=0
---[ end trace 0e56686fd458f0c5 ]---
update e820 for mtrr
modified physical RAM map:
modified: [mem 0x0000000000000000-0x0000000000000fff] reserved
...
modified: [mem 0x00000000ff000000-0x000000207fffffff] reserved
last_pfn = 0x6354e max_arch_pfn = 0x10000000000
Memory KASLR using RDRAND RDTSC...
x2apic: enabled by BIOS, switching to x2apic ops
Using GB pages for direct mapping
...
Initmem setup node 0 [mem 0x0000000000001000-0x000000006354dfff]
DMA zone: 28769 pages in unavailable ranges
DMA32 zone: 19122 pages in unavailable ranges
BUG: unable to handle page fault for address: ff24b56eba60cff8
BAD
Oops: 0000 [#1] SMP NOPTI
CPU: 0 PID: 0 Comm: swapper Tainted: G W 5.10.50 #2
...
Call Trace:
? set_pte_vaddr_p4d+0x24/0x35
? __native_set_fixmap+0x21/0x28
? map_vsyscall+0x35/0x56
? setup_arch+0xa00/0xaed
? printk+0x53/0x6a
? start_kernel+0x55/0x507
? load_ucode_intel_bsp+0x1c/0x4d
? secondary_startup_64_no_verify+0xc2/0xcb
CR2: ff24b56eba60cff8
---[ end trace 0e56686fd458f0c6 ]---
RIP: 0010:fill_pud+0xa/0x62
...
Kernel panic - not syncing: Attempted to kill the idle task!
---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]---
Change-Id: Ib2a0e1f1f13e797c1fab6aca589d060c4d3fa15b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/uncore.c
6 files changed, 51 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83538/5
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
Patch Set 18:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83705/comment/7e20c288_0f0f4cde?us… :
PS16, Line 9: enables
> Isn’t it just adding a Kconfig symbol?
Ack
https://review.coreboot.org/c/coreboot/+/83705/comment/a032a8e6_cc215bb9?us… :
PS16, Line 10: when
> Fits on the line above.
Acknowledged
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/83705/comment/8edb0907_41895a68?us… :
PS16, Line 108: sign of life
> Sign-of-Life
Acknowledged
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Hello Angel Pons, Dinesh Gehlot, Paul Menzel, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch introduces a new early sign-of-life config option when
libgfx or uGOP is enabled for early graphics initialization.
BUG=NA
TEST=Able to build google/rex and google/tivviks
Cq-Depend: CB:83769, CB:83770
Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/vendorcode/google/chromeos/Kconfig
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/18
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Hello Angel Pons, Dinesh Gehlot, Paul Menzel, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch introduces a new early sign of life config option when
libgfx or uGOP is enabled for early graphics initialization.
BUG=NA
TEST=Able to build google/rex and google/tivviks
Cq-Depend: CB:83769, CB:83770
Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/vendorcode/google/chromeos/Kconfig
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/17
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Leo Chou has posted comments on this change by Leo Chou. ( https://review.coreboot.org/c/coreboot/+/83794?usp=email )
Change subject: mb/google/nissa/var/pujjoga: Modify P sensor setting
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83794/comment/ccef3c74_00815758?us… :
PS5, Line 11: PAD_CFG_GPI_APIC
> describe why original setting not work?
The original is input pin,not a ACPI irq pin,
This incorrect configuration prevents the CPU from entering the C8 state properly. thanks.
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