Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak.
Hello Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#12).
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Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp: Add PCIe root port driver
......................................................................
soc/intel/xeon_sp: Add PCIe root port driver
The driver sets ACPI names for PCIe root ports and its subordinate
devices, and fill SSDT for them accordingly. SPR PCIe root port
devices are initially supported.
TEST=Build and boot on intel/archercity CRB
Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/pcie_root_port.c
2 files changed, 92 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81567/12
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Nico Huber has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83796?usp=email )
Change subject: mb/starlabs/starlite_adl: Remove has_cdm from devicetree
......................................................................
Patch Set 1: Code-Review+2
(3 comments)
Patchset:
PS1:
Looks like Jenkins forgot to score.
Commit Message:
https://review.coreboot.org/c/coreboot/+/83796/comment/8cc07da7_0e8d6b38?us… :
PS1, Line 9: ;
*only*
https://review.coreboot.org/c/coreboot/+/83796/comment/1a6b3c99_d33d7a70?us… :
PS1, Line 10: that was merged only requires `cdm_index` so remove the former.
Could reference the merged commit.
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Change subject: i2c/drivers/generic: Add support for including a CDM
......................................................................
Patch Set 12:
(1 comment)
Patchset:
PS2:
> ACPI spec says _CDM is the clock domain, I can't find anything on MS' site about chip direct mapping […]
It's hard to believe that Microsoft would violate the spec like this. Is this
really about Windows or rather a 3rd-party driver?
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Change subject: soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/gpmr.h:
https://review.coreboot.org/c/coreboot/+/83317/comment/a8ec550e_1ce68fc7?us… :
PS3, Line 10: #include <soc/gpmr.h>
> From the help message in src/soc/intel/common/block/ioc/Kconfig, IOC replaces DMI interface starting […]
Can we rename to, e.g. USE_SOC_PCR_GPMR_DEFINITION and handle in pcr_gpmr.h?
e.g.
#if CONFIG(USE_SOC_PCR_GPMR_DEFINITION)
#include <soc/pcr_gpmr.h>
#else
...
#endif
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Attention is currently required from: Tongtong Pan.
Tongtong Pan has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/83790?usp=email )
Change subject: mb/google/dedede:Add fw_config control to wifi driver
......................................................................
mb/google/dedede:Add fw_config control to wifi driver
BUG=b:351968527
Change-Id: I4c7e2fb6fe38c048f29cb8255c4b125ea284de5b
Signed-off-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
M src/mainboard/google/dedede/variants/awasuki/ramstage.c
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
M src/soc/intel/jasperlake/chip.h
5 files changed, 62 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/83790/3
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Change subject: drivers/intel/fsp2: Add config for FSP uGOP eSOL
......................................................................
Patch Set 7:
(3 comments)
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/83770/comment/e3c7f8b6_05dd2f2f?us… :
PS6, Line 477: sign of life
> In the current code base it’s spelled Sign-of-Life. (No idea, if we should stay consistent. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83770/comment/494bbcf0_6d5357fd?us… :
PS6, Line 475: Enable the FSP-M Sign-of-Life feature to display a text message
: on screen during memory training and CSME update. This utilizes Intel's underlying uGOP
: technology to enable early sign of life (eSOL) as part of FSP-M.
> Please re-flow.
Acknowledged
https://review.coreboot.org/c/coreboot/+/83770/comment/64c72d39_bb6e4d07?us… :
PS6, Line 476: This utilizes Intel's underlying uGOP
: technology
> Is this too much marketing speech? Maybe: […]
Acknowledged
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Hello Andrey Petrov, Dinesh Gehlot, Ronak Kanabar, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83770?usp=email
to look at the new patch set (#7).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2: Add config for FSP uGOP eSOL
......................................................................
drivers/intel/fsp2: Add config for FSP uGOP eSOL
This patch introduces a new configuration option,
FSP_UGOP_EARLY_SIGN_OF_LIFE, to the FSP driver. This enables uGOP
support using FSP-M for the early sign-of-life feature in SOC.
BUG=NA
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ic0426ff7974a141ae9188b0098677b4cc97aee36
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/drivers/intel/fsp2_0/Kconfig
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/83770/7
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